diff mbox series

[RFT,05/14] drm/msm/a6xx: Resolve the meaning of AMSBC

Message ID 20250508-topic-ubwc_central-v1-5-035c4c5cbe50@oss.qualcomm.com
State New
Headers show
Series Add a single source of truth for UBWC configuration data | expand

Commit Message

Konrad Dybcio May 8, 2025, 6:12 p.m. UTC 
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

The bit must be set to 1 if the UBWC encoder version is >= 3.0, drop it
as a separate field.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

Comments

Connor Abbott May 8, 2025, 7:16 p.m. UTC | #1 
On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> The bit must be set to 1 if the UBWC encoder version is >= 3.0, drop it
> as a separate field.

For these sorts of things, it's probably best to add a helper to the
common ubwc config header. Other blocks also have bits for enabling
AMSBC and similar things that also need to be set based on the UBWC
version.

Connor

>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++---------
>  1 file changed, 3 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 89eb725f0950f3679d6214366cfbd22d5bcf4bc7..5fe0e8e72930320282a856e1ff77994865360854 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -617,21 +617,16 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>
>         if (adreno_is_a621(gpu)) {
>                 gpu->ubwc_config.highest_bank_bit = 0;
> -               gpu->ubwc_config.amsbc = 1;
>                 gpu->ubwc_config.uavflagprd_inv = 2;
>         }
>
>         if (adreno_is_a623(gpu)) {
>                 gpu->ubwc_config.highest_bank_bit = 3;
> -               gpu->ubwc_config.amsbc = 1;
>                 gpu->ubwc_config.rgb565_predicator = 1;
>                 gpu->ubwc_config.uavflagprd_inv = 2;
>                 gpu->ubwc_config.macrotile_mode = 1;
>         }
>
> -       if (adreno_is_a640_family(gpu))
> -               gpu->ubwc_config.amsbc = 1;
> -
>         if (adreno_is_a680(gpu))
>                 gpu->ubwc_config.macrotile_mode = 1;
>
> @@ -642,7 +637,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>             adreno_is_a740_family(gpu)) {
>                 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
>                 gpu->ubwc_config.highest_bank_bit = 3;
> -               gpu->ubwc_config.amsbc = 1;
>                 gpu->ubwc_config.rgb565_predicator = 1;
>                 gpu->ubwc_config.uavflagprd_inv = 2;
>                 gpu->ubwc_config.macrotile_mode = 1;
> @@ -650,7 +644,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>
>         if (adreno_is_a663(gpu)) {
>                 gpu->ubwc_config.highest_bank_bit = 0;
> -               gpu->ubwc_config.amsbc = 1;
>                 gpu->ubwc_config.rgb565_predicator = 1;
>                 gpu->ubwc_config.uavflagprd_inv = 2;
>                 gpu->ubwc_config.macrotile_mode = 1;
> @@ -659,7 +652,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>
>         if (adreno_is_7c3(gpu)) {
>                 gpu->ubwc_config.highest_bank_bit = 1;
> -               gpu->ubwc_config.amsbc = 1;
>                 gpu->ubwc_config.uavflagprd_inv = 2;
>                 gpu->ubwc_config.macrotile_mode = 1;
>         }
> @@ -675,7 +667,9 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>  static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
>  {
>         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> +       const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg;
>         u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit;
> +       bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
>         u32 hbb_hi = hbb >> 2;
>         u32 hbb_lo = hbb & 3;
>         u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
> @@ -684,7 +678,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
>         gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
>                   level2_swizzling_dis << 12 |
>                   adreno_gpu->ubwc_config.rgb565_predicator << 11 |
> -                 hbb_hi << 10 | adreno_gpu->ubwc_config.amsbc << 4 |
> +                 hbb_hi << 10 | amsbc << 4 |
>                   adreno_gpu->ubwc_config.min_acc_len << 3 |
>                   hbb_lo << 1 | ubwc_mode);
>
>
> --
> 2.49.0
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 89eb725f0950f3679d6214366cfbd22d5bcf4bc7..5fe0e8e72930320282a856e1ff77994865360854 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -617,21 +617,16 @@  static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
 
 	if (adreno_is_a621(gpu)) {
 		gpu->ubwc_config.highest_bank_bit = 0;
-		gpu->ubwc_config.amsbc = 1;
 		gpu->ubwc_config.uavflagprd_inv = 2;
 	}
 
 	if (adreno_is_a623(gpu)) {
 		gpu->ubwc_config.highest_bank_bit = 3;
-		gpu->ubwc_config.amsbc = 1;
 		gpu->ubwc_config.rgb565_predicator = 1;
 		gpu->ubwc_config.uavflagprd_inv = 2;
 		gpu->ubwc_config.macrotile_mode = 1;
 	}
 
-	if (adreno_is_a640_family(gpu))
-		gpu->ubwc_config.amsbc = 1;
-
 	if (adreno_is_a680(gpu))
 		gpu->ubwc_config.macrotile_mode = 1;
 
@@ -642,7 +637,6 @@  static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
 	    adreno_is_a740_family(gpu)) {
 		/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
 		gpu->ubwc_config.highest_bank_bit = 3;
-		gpu->ubwc_config.amsbc = 1;
 		gpu->ubwc_config.rgb565_predicator = 1;
 		gpu->ubwc_config.uavflagprd_inv = 2;
 		gpu->ubwc_config.macrotile_mode = 1;
@@ -650,7 +644,6 @@  static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
 
 	if (adreno_is_a663(gpu)) {
 		gpu->ubwc_config.highest_bank_bit = 0;
-		gpu->ubwc_config.amsbc = 1;
 		gpu->ubwc_config.rgb565_predicator = 1;
 		gpu->ubwc_config.uavflagprd_inv = 2;
 		gpu->ubwc_config.macrotile_mode = 1;
@@ -659,7 +652,6 @@  static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
 
 	if (adreno_is_7c3(gpu)) {
 		gpu->ubwc_config.highest_bank_bit = 1;
-		gpu->ubwc_config.amsbc = 1;
 		gpu->ubwc_config.uavflagprd_inv = 2;
 		gpu->ubwc_config.macrotile_mode = 1;
 	}
@@ -675,7 +667,9 @@  static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
 static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
 {
 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+	const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg;
 	u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit;
+	bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
 	u32 hbb_hi = hbb >> 2;
 	u32 hbb_lo = hbb & 3;
 	u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
@@ -684,7 +678,7 @@  static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
 	gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
 		  level2_swizzling_dis << 12 |
 		  adreno_gpu->ubwc_config.rgb565_predicator << 11 |
-		  hbb_hi << 10 | adreno_gpu->ubwc_config.amsbc << 4 |
+		  hbb_hi << 10 | amsbc << 4 |
 		  adreno_gpu->ubwc_config.min_acc_len << 3 |
 		  hbb_lo << 1 | ubwc_mode);