diff mbox series

[v4,20/27] target/i386/cpu: Remove CPUX86State::enable_l3_cache field

Message ID 20250508133550.81391-21-philmd@linaro.org
State New
Headers show
Series hw/i386/pc: Remove deprecated 2.6 and 2.7 PC machines | expand

Commit Message

Philippe Mathieu-Daudé May 8, 2025, 1:35 p.m. UTC 
The CPUX86State::enable_l3_cache boolean was only disabled
for the pc-q35-2.7 and pc-i440fx-2.7 machines, which got
removed.  Being now always %true, we can remove it and simplify
cpu_x86_cpuid() and encode_cache_cpuid80000006().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/i386/cpu.h |  6 ------
 target/i386/cpu.c | 39 +++++++++++++--------------------------
 2 files changed, 13 insertions(+), 32 deletions(-)

Comments

Zhao Liu May 9, 2025, 9:11 a.m. UTC | #1 
On Thu, May 08, 2025 at 03:35:43PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Thu,  8 May 2025 15:35:43 +0200
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [PATCH v4 20/27] target/i386/cpu: Remove
>  CPUX86State::enable_l3_cache field
> X-Mailer: git-send-email 2.47.1
> 
> The CPUX86State::enable_l3_cache boolean was only disabled
> for the pc-q35-2.7 and pc-i440fx-2.7 machines, which got
> removed.  Being now always %true, we can remove it and simplify
> cpu_x86_cpuid() and encode_cache_cpuid80000006().
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/i386/cpu.h |  6 ------
>  target/i386/cpu.c | 39 +++++++++++++--------------------------
>  2 files changed, 13 insertions(+), 32 deletions(-)
> 
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index b5cbd91c156..62239b0a562 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -2219,12 +2219,6 @@ struct ArchCPU {
>       */
>      bool enable_lmce;
>  
> -    /* Compatibility bits for old machine types.
> -     * If true present virtual l3 cache for VM, the vcpus in the same virtual
> -     * socket share an virtual l3 cache.
> -     */
> -    bool enable_l3_cache;
> -
>      /* Compatibility bits for old machine types.
>       * If true present L1 cache as per-thread, not per-core.
>       */

I realize this is another special case.

There is no support for hybrid x86 CPUs in QEMU, but it's also true that
there are some actual modern x86 Client CPUs without l3 cache, such as
Intel MTL's low power E core (and it has vmx support, i.e., support KVM).

So I think we can keep this property as well, to have some more
configuration options for users' emulation.
diff mbox series

Patch

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index b5cbd91c156..62239b0a562 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2219,12 +2219,6 @@  struct ArchCPU {
      */
     bool enable_lmce;
 
-    /* Compatibility bits for old machine types.
-     * If true present virtual l3 cache for VM, the vcpus in the same virtual
-     * socket share an virtual l3 cache.
-     */
-    bool enable_l3_cache;
-
     /* Compatibility bits for old machine types.
      * If true present L1 cache as per-thread, not per-core.
      */
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6b9a1f2251a..4be174ea9c7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -468,17 +468,13 @@  static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
            (AMD_ENC_ASSOC(l2->associativity) << 12) |
            (l2->lines_per_tag << 8) | (l2->line_size);
 
-    if (l3) {
-        assert(l3->size % (512 * 1024) == 0);
-        assert(l3->associativity > 0);
-        assert(l3->lines_per_tag > 0);
-        assert(l3->line_size > 0);
-        *edx = ((l3->size / (512 * 1024)) << 18) |
-               (AMD_ENC_ASSOC(l3->associativity) << 12) |
-               (l3->lines_per_tag << 8) | (l3->line_size);
-    } else {
-        *edx = 0;
-    }
+    assert(l3->size % (512 * 1024) == 0);
+    assert(l3->associativity > 0);
+    assert(l3->lines_per_tag > 0);
+    assert(l3->line_size > 0);
+    *edx = ((l3->size / (512 * 1024)) << 18) |
+           (AMD_ENC_ASSOC(l3->associativity) << 12) |
+           (l3->lines_per_tag << 8) | (l3->line_size);
 }
 
 /* Encode cache info for CPUID[8000001D] */
@@ -6849,11 +6845,7 @@  void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
         }
         *eax = 1; /* Number of CPUID[EAX=2] calls required */
         *ebx = 0;
-        if (!cpu->enable_l3_cache) {
-            *ecx = 0;
-        } else {
-            *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
-        }
+        *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
         *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
                (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) <<  8) |
                (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
@@ -6907,13 +6899,10 @@  void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
                                     eax, ebx, ecx, edx);
                 break;
             case 3: /* L3 cache info */
-                if (cpu->enable_l3_cache) {
-                    encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
-                                        topo_info,
-                                        eax, ebx, ecx, edx);
-                    break;
-                }
-                /* fall through */
+                encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
+                                    topo_info,
+                                    eax, ebx, ecx, edx);
+                break;
             default: /* end of info */
                 *eax = *ebx = *ecx = *edx = 0;
                 break;
@@ -7284,8 +7273,7 @@  void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
                (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
                (L2_ITLB_4K_ENTRIES);
         encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
-                                   cpu->enable_l3_cache ?
-                                   env->cache_info_amd.l3_cache : NULL,
+                                   env->cache_info_amd.l3_cache,
                                    ecx, edx);
         break;
     case 0x80000007:
@@ -8821,7 +8809,6 @@  static const Property x86_cpu_properties[] = {
     DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true),
     DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true),
     DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
-    DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
     DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid,
                      false),
     DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),