| Message ID | 20250508133550.81391-14-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | hw/i386/pc: Remove deprecated 2.6 and 2.7 PC machines | expand |
On Thu, May 08, 2025 at 03:35:36PM +0200, Philippe Mathieu-Daudé wrote: > Date: Thu, 8 May 2025 15:35:36 +0200 > From: Philippe Mathieu-Daudé <philmd@linaro.org> > Subject: [PATCH v4 13/27] target/i386/cpu: Remove > CPUX86State::fill_mtrr_mask field > X-Mailer: git-send-email 2.47.1 > > The CPUX86State::fill_mtrr_mask boolean was only disabled > for the pc-q35-2.6 and pc-i440fx-2.6 machines, which got > removed. Being now always %true, we can remove it and simplify > kvm_get_msrs(). > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/i386/cpu.h | 3 --- > target/i386/cpu.c | 1 - > target/i386/kvm/kvm.c | 10 +++------- > 3 files changed, 3 insertions(+), 11 deletions(-) No case found for external user use, so, Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
On Thu, 8 May 2025 15:35:36 +0200 Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > The CPUX86State::fill_mtrr_mask boolean was only disabled > for the pc-q35-2.6 and pc-i440fx-2.6 machines, which got > removed. Being now always %true, we can remove it and simplify > kvm_get_msrs(). > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/i386/cpu.h | 3 --- > target/i386/cpu.c | 1 - > target/i386/kvm/kvm.c | 10 +++------- > 3 files changed, 3 insertions(+), 11 deletions(-) > > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 06817a31cf9..7585407da54 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -2253,9 +2253,6 @@ struct ArchCPU { > /* Enable auto level-increase for Intel Processor Trace leave */ > bool intel_pt_auto_level; > > - /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ > - bool fill_mtrr_mask; > - > /* if true override the phys_bits value with a value read from the host */ > bool host_phys_bits; > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 6fe37f71b1e..fb505d13122 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -8810,7 +8810,6 @@ static const Property x86_cpu_properties[] = { > DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), > DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), > DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), > - DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), same as previous patch, deprecate 1st then remove > DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, > UINT32_MAX), > DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), > diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c > index c9a3c02e3e3..87edce99e85 100644 > --- a/target/i386/kvm/kvm.c > +++ b/target/i386/kvm/kvm.c > @@ -4635,13 +4635,9 @@ static int kvm_get_msrs(X86CPU *cpu) > * we're migrating to. > */ > > - if (cpu->fill_mtrr_mask) { > - QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52); > - assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS); > - mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits); > - } else { > - mtrr_top_bits = 0; > - } > + QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52); > + assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS); > + mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits); > > for (i = 0; i < ret; i++) { > uint32_t index = msrs[i].index;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 06817a31cf9..7585407da54 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2253,9 +2253,6 @@ struct ArchCPU { /* Enable auto level-increase for Intel Processor Trace leave */ bool intel_pt_auto_level; - /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ - bool fill_mtrr_mask; - /* if true override the phys_bits value with a value read from the host */ bool host_phys_bits; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6fe37f71b1e..fb505d13122 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8810,7 +8810,6 @@ static const Property x86_cpu_properties[] = { DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), - DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, UINT32_MAX), DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index c9a3c02e3e3..87edce99e85 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4635,13 +4635,9 @@ static int kvm_get_msrs(X86CPU *cpu) * we're migrating to. */ - if (cpu->fill_mtrr_mask) { - QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52); - assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS); - mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits); - } else { - mtrr_top_bits = 0; - } + QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52); + assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS); + mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits); for (i = 0; i < ret; i++) { uint32_t index = msrs[i].index;
The CPUX86State::fill_mtrr_mask boolean was only disabled for the pc-q35-2.6 and pc-i440fx-2.6 machines, which got removed. Being now always %true, we can remove it and simplify kvm_get_msrs(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/i386/cpu.h | 3 --- target/i386/cpu.c | 1 - target/i386/kvm/kvm.c | 10 +++------- 3 files changed, 3 insertions(+), 11 deletions(-)