@@ -256,7 +256,9 @@ static inline void iwl_bios_setup_step(struct iwl_trans *trans,
if (iwl_bios_get_dsbr(fwrt, &dsbr))
dsbr = 0;
- trans->dsbr_urm_fw_dependent = !!(dsbr & IWL_DSBR_FW_MODIFIED_URM_MASK);
- trans->dsbr_urm_permanent = !!(dsbr & IWL_DSBR_PERMANENT_URM_MASK);
+ trans->conf.dsbr_urm_fw_dependent =
+ !!(dsbr & IWL_DSBR_FW_MODIFIED_URM_MASK);
+ trans->conf.dsbr_urm_permanent =
+ !!(dsbr & IWL_DSBR_PERMANENT_URM_MASK);
}
#endif /* __fw_regulatory_h__ */
@@ -310,11 +310,12 @@ static int iwl_uefi_step_parse(struct uefi_cnv_common_step_data *common_step_dat
if (common_step_data->revision != 1)
return -EINVAL;
- trans->mbx_addr_0_step = (u32)common_step_data->revision |
+ trans->conf.mbx_addr_0_step =
+ (u32)common_step_data->revision |
(u32)common_step_data->cnvi_eq_channel << 8 |
(u32)common_step_data->cnvr_eq_channel << 16 |
(u32)common_step_data->radio1 << 24;
- trans->mbx_addr_1_step = (u32)common_step_data->radio2;
+ trans->conf.mbx_addr_1_step = (u32)common_step_data->radio2;
return 0;
}
@@ -341,6 +341,4 @@ iwl_trans_pcie_ctx_info_gen3_load_reduce_power(struct iwl_trans *trans,
void
iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans,
const struct iwl_ucode_capabilities *capa);
-int iwl_trans_pcie_ctx_info_gen3_set_step(struct iwl_trans *trans,
- u32 mbx_addr_0_step, u32 mbx_addr_1_step);
#endif /* __iwl_context_info_file_gen3_h__ */
@@ -417,6 +417,10 @@ struct iwl_dump_sanitize_ops {
* starting the firmware, used for tracing
* @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the
* start of the 802.11 header in the @rx_mpdu_cmd
+ * @dsbr_urm_fw_dependent: switch to URM based on fw settings
+ * @dsbr_urm_permanent: switch to URM permanently
+ * @mbx_addr_0_step: step address data 0
+ * @mbx_addr_1_step: step address data 1
*/
struct iwl_trans_config {
u8 cmd_queue;
@@ -435,6 +439,12 @@ struct iwl_trans_config {
bool wide_cmd_header;
u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;
+
+ u8 dsbr_urm_fw_dependent:1,
+ dsbr_urm_permanent:1;
+
+ u32 mbx_addr_0_step;
+ u32 mbx_addr_1_step;
};
struct iwl_trans_dump_data {
@@ -865,8 +875,6 @@ struct iwl_trans_info {
* @sync_cmd_lockdep_map: lockdep map for checking sync commands
* @dbg: additional debug data, see &struct iwl_trans_debug
* @init_dram: FW initialization DMA data
- * @mbx_addr_0_step: step address data 0
- * @mbx_addr_1_step: step address data 1
* @reduced_cap_sku: reduced capability supported SKU
* @step_urm: STEP is in URM, no support for MCS>9 in 320 MHz
* @restart: restart worker data
@@ -874,8 +882,6 @@ struct iwl_trans_info {
* @restart.mode: reset/restart error mode information
* @restart.during_reset: error occurred during previous software reset
* @trans_specific: data for the specific transport this is allocated for/with
- * @dsbr_urm_fw_dependent: switch to URM based on fw settings
- * @dsbr_urm_permanent: switch to URM permanently
* @ext_32khz_clock_valid: if true, the external 32 KHz clock can be used
* @request_top_reset: TOP reset was requested, used by the reset
* worker that should be scheduled (with appropriate reason)
@@ -899,9 +905,6 @@ struct iwl_trans {
bool reduced_cap_sku;
bool step_urm;
- u8 dsbr_urm_fw_dependent:1,
- dsbr_urm_permanent:1;
-
bool ext_32khz_clock_valid;
bool pm_support;
@@ -924,9 +927,6 @@ struct iwl_trans {
struct iwl_trans_debug dbg;
struct iwl_self_init_dram init_dram;
- u32 mbx_addr_0_step;
- u32 mbx_addr_1_step;
-
struct {
struct delayed_work wk;
struct iwl_fw_error_dump_mode mode;
@@ -325,10 +325,13 @@ EXPORT_SYMBOL_IF_IWLWIFI_KUNIT(global_iwl_mld_goups_size);
static void
iwl_mld_configure_trans(struct iwl_op_mode *op_mode)
{
- const struct iwl_mld *mld = IWL_OP_MODE_GET_MLD(op_mode);
+ struct iwl_mld *mld = IWL_OP_MODE_GET_MLD(op_mode);
static const u8 no_reclaim_cmds[] = {TX_CMD};
struct iwl_trans *trans = mld->trans;
+ iwl_bios_setup_step(trans, &mld->fwrt);
+ iwl_uefi_get_step_table(trans);
+
trans->conf.rx_buf_size = iwl_amsdu_size_to_rxb_size();
trans->conf.command_groups = iwl_mld_groups;
trans->conf.command_groups_size = ARRAY_SIZE(iwl_mld_groups);
@@ -388,12 +391,10 @@ iwl_op_mode_mld_start(struct iwl_trans *trans, const struct iwl_cfg *cfg,
iwl_mld_get_bios_tables(mld);
iwl_uefi_get_sgom_table(trans, &mld->fwrt);
- iwl_uefi_get_step_table(trans);
if (iwl_bios_get_eckv(&mld->fwrt, &eckv_value))
IWL_DEBUG_RADIO(mld, "ECKV table doesn't exist in BIOS\n");
else
trans->ext_32khz_clock_valid = !!eckv_value;
- iwl_bios_setup_step(trans, &mld->fwrt);
mld->bios_enable_puncturing = iwl_uefi_get_puncturing(&mld->fwrt);
iwl_mld_hw_set_regulatory(mld);
@@ -132,10 +132,10 @@ int iwl_pcie_ctxt_info_gen3_alloc(struct iwl_trans *trans,
break;
}
- if (trans->dsbr_urm_fw_dependent)
+ if (trans->conf.dsbr_urm_fw_dependent)
control_flags_ext |= IWL_PRPH_SCRATCH_EXT_URM_FW;
- if (trans->dsbr_urm_permanent)
+ if (trans->conf.dsbr_urm_permanent)
control_flags_ext |= IWL_PRPH_SCRATCH_EXT_URM_PERM;
if (trans->ext_32khz_clock_valid)
@@ -184,8 +184,10 @@ int iwl_pcie_ctxt_info_gen3_alloc(struct iwl_trans *trans,
prph_sc_ctrl->control.control_flags_ext = cpu_to_le32(control_flags_ext);
/* initialize the Step equalizer data */
- prph_sc_ctrl->step_cfg.mbx_addr_0 = cpu_to_le32(trans->mbx_addr_0_step);
- prph_sc_ctrl->step_cfg.mbx_addr_1 = cpu_to_le32(trans->mbx_addr_1_step);
+ prph_sc_ctrl->step_cfg.mbx_addr_0 =
+ cpu_to_le32(trans->conf.mbx_addr_0_step);
+ prph_sc_ctrl->step_cfg.mbx_addr_1 =
+ cpu_to_le32(trans->conf.mbx_addr_1_step);
/* allocate ucode sections in dram and set addresses */
ret = iwl_pcie_init_fw_sec(trans, img, &prph_scratch->dram.common);