@@ -304,7 +304,6 @@ enum iwl_pcie_imr_status {
* @cmd: command queue data
* @cmd.fifo: FIFO number
* @cmd.q_id: queue ID
- * @cmd.wdg_timeout: watchdog timeout
* @tfd: TFD data
* @tfd.max_tbs: max number of buffers per TFD
* @tfd.size: TFD size
@@ -324,7 +323,6 @@ struct iwl_pcie_txqs {
struct {
u8 fifo;
u8 q_id;
- unsigned int wdg_timeout;
} cmd;
struct {
@@ -3845,9 +3845,6 @@ iwl_trans_pcie_alloc(struct pci_dev *pdev,
}
trans->max_skb_frags = IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie);
- /* Set a short watchdog for the command queue */
- trans_pcie->txqs.cmd.wdg_timeout = IWL_DEF_WD_TIMEOUT;
-
trans_pcie->txqs.tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
if (!trans_pcie->txqs.tso_hdr_page) {
ret = -ENOMEM;
@@ -514,7 +514,7 @@ void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
iwl_trans_ac_txq_enable(trans, trans_pcie->txqs.cmd.q_id,
trans_pcie->txqs.cmd.fifo,
- trans_pcie->txqs.cmd.wdg_timeout);
+ IWL_DEF_WD_TIMEOUT);
/* Activate all Tx DMA/FIFO channels */
iwl_scd_activate_fifos(trans);