diff mbox series

[RFT,v6,2/5] drm/msm/adreno: Add speedbin data for SM8550 / A740

Message ID 20250430-topic-smem_speedbin_respin-v6-2-954ff66061cf@oss.qualcomm.com
State New
Headers show
Series Add SMEM-based speedbin matching | expand

Commit Message

Konrad Dybcio April 30, 2025, 11:34 a.m. UTC 
From: Konrad Dybcio <konrad.dybcio@linaro.org>

Add speebin data for A740, as found on SM8550 and derivative SoCs.

For non-development SoCs it seems that "everything except FC_AC, FC_AF
should be speedbin 1", but what the values are for said "everything" are
not known, so that's an exercise left to the user..

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Akhil P Oommen May 11, 2025, 9:51 a.m. UTC | #1 
On 5/1/2025 9:23 PM, Konrad Dybcio wrote:
> On 5/1/25 11:29 AM, Akhil P Oommen wrote:
>> On 4/30/2025 10:26 PM, neil.armstrong@linaro.org wrote:
>>> On 30/04/2025 18:39, Konrad Dybcio wrote:
>>>> On 4/30/25 6:19 PM, neil.armstrong@linaro.org wrote:
>>>>> On 30/04/2025 17:36, Konrad Dybcio wrote:
>>>>>> On 4/30/25 4:49 PM, neil.armstrong@linaro.org wrote:
>>>>>>> On 30/04/2025 15:09, Konrad Dybcio wrote:
>>>>>>>> On 4/30/25 2:49 PM, neil.armstrong@linaro.org wrote:
>>>>>>>>> On 30/04/2025 14:35, Konrad Dybcio wrote:
>>>>>>>>>> On 4/30/25 2:26 PM, neil.armstrong@linaro.org wrote:
> 
> [...]
> 
>>> This behaves exactly as I said, so please fix it.
> 
> Eh, I was so sure I tested things correctly..
> 
>>
>> Konrad,
>>
>> iirc, we discussed this in one of the earlier revision. There is a
>> circular dependency between the driver change for SKU support and the dt
>> change that adds supported_hw bitmask in opp-table. Only scenario it
>> works is when you add these to the initial patches series of a new GPU.
>>
>> It will be very useful if we can break this circular dependency.
> 
> Right. Let's start with getting that in order

Another complication with the socinfo is that the value is unique for a
chipset, not for a GPU. So, it won't work if we keep this data in GPU
list in the driver.

Downstream solved this problem by keeping the PCODE/FCODE mappings in
the devicetree.

-Akhil.

> 
> Konrad
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 53e2ff4406d8f0afe474aaafbf0e459ef8f4577d..61daa331567925e529deae5e25d6fb63a8ba8375 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -11,6 +11,9 @@ 
 #include "a6xx.xml.h"
 #include "a6xx_gmu.xml.h"
 
+#include <linux/soc/qcom/smem.h>
+#include <linux/soc/qcom/socinfo.h>
+
 static const struct adreno_reglist a612_hwcg[] = {
 	{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
 	{REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
@@ -1431,6 +1434,11 @@  static const struct adreno_info a7xx_gpus[] = {
 		},
 		.address_space_size = SZ_16G,
 		.preempt_record_size = 4192 * SZ_1K,
+		.speedbins = ADRENO_SPEEDBINS(
+			{ ADRENO_SKU_ID(SOCINFO_FC_AC), 0 },
+			{ ADRENO_SKU_ID(SOCINFO_FC_AF), 0 },
+			/* Other feature codes (on prod SoCs) should match to speedbin 1 */
+		),
 	}, {
 		.chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */
 		.family = ADRENO_7XX_GEN2,