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[RFT,v6,3/5] drm/msm/adreno: Define A530 speed bins explicitly

Message ID 20250430-topic-smem_speedbin_respin-v6-3-954ff66061cf@oss.qualcomm.com
State New
Headers show
Series [RFT,v6,1/5] drm/msm/adreno: Implement SMEM-based speed bin | expand

Commit Message

Konrad Dybcio April 30, 2025, 11:34 a.m. UTC 
From: Konrad Dybcio <konrad.dybcio@linaro.org>

In preparation for commonizing the speedbin handling code.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 6 ++++++
 1 file changed, 6 insertions(+)
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Patch

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c
index 633f3153916277b34f90acc046ed2ee04a761727..105b3d14bd7592c784863346cfbcc28f000c2e8f 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c
@@ -129,6 +129,12 @@  static const struct adreno_info a5xx_gpus[] = {
 			ADRENO_QUIRK_FAULT_DETECT_MASK,
 		.init = a5xx_gpu_init,
 		.zapfw = "a530_zap.mdt",
+		.speedbins = ADRENO_SPEEDBINS(
+			{ 0, 0 },
+			{ 1, 1 },
+			{ 2, 2 },
+			{ 3, 3 },
+		),
 	}, {
 		.chip_ids = ADRENO_CHIP_IDS(0x05040001),
 		.family = ADRENO_5XX,