| Message ID | 20250425-sm6350-gdsc-val-v1-0-1f252d9c5e4e@fairphone.com |
|---|---|
| State | New |
| Headers | show |
On Fri, 25 Apr 2025 14:12:54 +0200, Luca Weiss wrote: > As described in the commit messages, keep the GDSC configs aligned with > the downstream kernel. > > For reference, this was checked using the following code: > > To: Bjorn Andersson <andersson@kernel.org> > To: Michael Turquette <mturquette@baylibre.com> > To: Stephen Boyd <sboyd@kernel.org> > To: Konrad Dybcio <konradybcio@kernel.org> > To: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > Cc: ~postmarketos/upstreaming@lists.sr.ht > Cc: phone-devel@vger.kernel.org > Cc: linux-arm-msm@vger.kernel.org > Cc: linux-clk@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > > [...] Applied, thanks! [0/4] Add *_wait_val values for GDSCs in all SM6350 clock drivers (no commit info) [1/4] clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs commit: e7b1c13280ad866f3b935f6c658713c41db61635 [2/4] clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs commit: 673989d27123618afab56df1143a75454178b4ae [3/4] clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs commit: afdfd829a99e467869e3ca1955fb6c6e337c340a [4/4] clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs commit: d988b0b866c2aeb23aa74022b5bbd463165a7a33 Best regards,
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index fa5fe4c2a2ee..049fcbefba50 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -402,7 +402,7 @@ static bool gdsc_get_hwmode(struct generic_pm_domain *domain, struct device *dev static int gdsc_init(struct gdsc *sc) { - u32 mask, val; + u32 mask, val, tmp; int on, ret; /* @@ -420,6 +420,14 @@ static int gdsc_init(struct gdsc *sc) if (!sc->clk_dis_wait_val) sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL; + regmap_read(sc->regmap, sc->gdscr, &tmp); + if (sc->en_rest_wait_val != ((tmp >> EN_REST_WAIT_SHIFT) & 0xf)) + printk(KERN_ERR "gdsc_init: %s en_rest_wait_val mismatch: (new) 0x%x vs 0x%x (reset)\n", sc->pd.name, sc->en_rest_wait_val, (tmp >> EN_REST_WAIT_SHIFT) & 0xf); + if (sc->en_few_wait_val != ((tmp >> EN_FEW_WAIT_SHIFT) & 0xf)) + printk(KERN_ERR "gdsc_init: %s en_few_wait_val mismatch: (new) 0x%x vs 0x%x (reset)\n", sc->pd.name, sc->en_few_wait_val, (tmp >> EN_FEW_WAIT_SHIFT) & 0xf); + if (sc->clk_dis_wait_val != ((tmp >> CLK_DIS_WAIT_SHIFT) & 0xf)) + printk(KERN_ERR "gdsc_init: %s clk_dis_wait_val mismatch: (new) 0x%x vs 0x%x (reset)\n", sc->pd.name, sc->clk_dis_wait_val, (tmp >> CLK_DIS_WAIT_SHIFT) & 0xf); + val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT | sc->en_few_wait_val << EN_FEW_WAIT_SHIFT | sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT;
As described in the commit messages, keep the GDSC configs aligned with the downstream kernel. For reference, this was checked using the following code: To: Bjorn Andersson <andersson@kernel.org> To: Michael Turquette <mturquette@baylibre.com> To: Stephen Boyd <sboyd@kernel.org> To: Konrad Dybcio <konradybcio@kernel.org> To: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Cc: ~postmarketos/upstreaming@lists.sr.ht Cc: phone-devel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> --- Luca Weiss (4): clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs drivers/clk/qcom/camcc-sm6350.c | 18 ++++++++++++++++++ drivers/clk/qcom/dispcc-sm6350.c | 3 +++ drivers/clk/qcom/gcc-sm6350.c | 6 ++++++ drivers/clk/qcom/gpucc-sm6350.c | 6 ++++++ 4 files changed, 33 insertions(+) --- base-commit: 9c32cda43eb78f78c73aee4aa344b777714e259b change-id: 20250425-sm6350-gdsc-val-a0162752854f Best regards,