| Message ID | 20250425152311.804338-5-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Fix write_misa vs aligned next_pc | expand |
On 25/4/25 17:23, Richard Henderson wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/riscv/cpu.h | 8 ++++---- > hw/riscv/riscv_hart.c | 2 +- > target/riscv/csr.c | 8 ++++---- > target/riscv/op_helper.c | 4 ++-- > 4 files changed, 11 insertions(+), 11 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
On Sat, Apr 26, 2025 at 1:26 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.h | 8 ++++---- > hw/riscv/riscv_hart.c | 2 +- > target/riscv/csr.c | 8 ++++---- > target/riscv/op_helper.c | 4 ++-- > 4 files changed, 11 insertions(+), 11 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 4d41a66d72..2c0524d0be 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -816,8 +816,8 @@ RISCVException riscv_csrr(CPURISCVState *env, int csrno, > target_ulong *ret_value); > > RISCVException riscv_csrrw(CPURISCVState *env, int csrno, > - target_ulong *ret_value, > - target_ulong new_value, target_ulong write_mask); > + target_ulong *ret_value, target_ulong new_value, > + target_ulong write_mask, uintptr_t ra); > RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, > target_ulong *ret_value, > target_ulong new_value, > @@ -826,13 +826,13 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, > static inline void riscv_csr_write(CPURISCVState *env, int csrno, > target_ulong val) > { > - riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); > + riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0); > } > > static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) > { > target_ulong val = 0; > - riscv_csrrw(env, csrno, &val, 0, 0); > + riscv_csrrw(env, csrno, &val, 0, 0, 0); > return val; > } > > diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c > index a55d156668..2ebbf41b18 100644 > --- a/hw/riscv/riscv_hart.c > +++ b/hw/riscv/riscv_hart.c > @@ -72,7 +72,7 @@ static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val) > ret = riscv_csrr(env, csrno, (target_ulong *)val); > } else if (strcmp(cmd, "set_csr") == 0) { > ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, > - MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); > + MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0); > } > > g_assert(ret == RISCV_EXCP_NONE); > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index d62d1aaaee..097640e25d 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -5574,15 +5574,15 @@ RISCVException riscv_csrr(CPURISCVState *env, int csrno, > } > > RISCVException riscv_csrrw(CPURISCVState *env, int csrno, > - target_ulong *ret_value, > - target_ulong new_value, target_ulong write_mask) > + target_ulong *ret_value, target_ulong new_value, > + target_ulong write_mask, uintptr_t ra) > { > RISCVException ret = riscv_csrrw_check(env, csrno, true); > if (ret != RISCV_EXCP_NONE) { > return ret; > } > > - return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, 0); > + return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, ra); > } > > static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, > @@ -5704,7 +5704,7 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, > if (!write_mask) { > ret = riscv_csrr(env, csrno, ret_value); > } else { > - ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); > + ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask, 0); > } > #if !defined(CONFIG_USER_ONLY) > env->debugger = false; > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index 5b0db2c45a..aee16e2e3a 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -71,7 +71,7 @@ target_ulong helper_csrr(CPURISCVState *env, int csr) > void helper_csrw(CPURISCVState *env, int csr, target_ulong src) > { > target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1; > - RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask); > + RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask, GETPC()); > > if (ret != RISCV_EXCP_NONE) { > riscv_raise_exception(env, ret, GETPC()); > @@ -82,7 +82,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr, > target_ulong src, target_ulong write_mask) > { > target_ulong val = 0; > - RISCVException ret = riscv_csrrw(env, csr, &val, src, write_mask); > + RISCVException ret = riscv_csrrw(env, csr, &val, src, write_mask, GETPC()); > > if (ret != RISCV_EXCP_NONE) { > riscv_raise_exception(env, ret, GETPC()); > -- > 2.43.0 > >
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4d41a66d72..2c0524d0be 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -816,8 +816,8 @@ RISCVException riscv_csrr(CPURISCVState *env, int csrno, target_ulong *ret_value); RISCVException riscv_csrrw(CPURISCVState *env, int csrno, - target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask); + target_ulong *ret_value, target_ulong new_value, + target_ulong write_mask, uintptr_t ra); RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, @@ -826,13 +826,13 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, static inline void riscv_csr_write(CPURISCVState *env, int csrno, target_ulong val) { - riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); + riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0); } static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) { target_ulong val = 0; - riscv_csrrw(env, csrno, &val, 0, 0); + riscv_csrrw(env, csrno, &val, 0, 0, 0); return val; } diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index a55d156668..2ebbf41b18 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -72,7 +72,7 @@ static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val) ret = riscv_csrr(env, csrno, (target_ulong *)val); } else if (strcmp(cmd, "set_csr") == 0) { ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, - MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); + MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0); } g_assert(ret == RISCV_EXCP_NONE); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d62d1aaaee..097640e25d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5574,15 +5574,15 @@ RISCVException riscv_csrr(CPURISCVState *env, int csrno, } RISCVException riscv_csrrw(CPURISCVState *env, int csrno, - target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask) + target_ulong *ret_value, target_ulong new_value, + target_ulong write_mask, uintptr_t ra) { RISCVException ret = riscv_csrrw_check(env, csrno, true); if (ret != RISCV_EXCP_NONE) { return ret; } - return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, 0); + return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, ra); } static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, @@ -5704,7 +5704,7 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, if (!write_mask) { ret = riscv_csrr(env, csrno, ret_value); } else { - ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); + ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask, 0); } #if !defined(CONFIG_USER_ONLY) env->debugger = false; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 5b0db2c45a..aee16e2e3a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -71,7 +71,7 @@ target_ulong helper_csrr(CPURISCVState *env, int csr) void helper_csrw(CPURISCVState *env, int csr, target_ulong src) { target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1; - RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask); + RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask, GETPC()); if (ret != RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); @@ -82,7 +82,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr, target_ulong src, target_ulong write_mask) { target_ulong val = 0; - RISCVException ret = riscv_csrrw(env, csr, &val, src, write_mask); + RISCVException ret = riscv_csrrw(env, csr, &val, src, write_mask, GETPC()); if (ret != RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC());
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/cpu.h | 8 ++++---- hw/riscv/riscv_hart.c | 2 +- target/riscv/csr.c | 8 ++++---- target/riscv/op_helper.c | 4 ++-- 4 files changed, 11 insertions(+), 11 deletions(-)