| Message ID | 20250425152311.804338-7-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Fix write_misa vs aligned next_pc | expand |
On 25/4/25 17:23, Richard Henderson wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/riscv/internals.h | 5 +++++ > target/riscv/translate.c | 5 ----- > 2 files changed, 5 insertions(+), 5 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
On Sat, Apr 26, 2025 at 1:24 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/internals.h | 5 +++++ > target/riscv/translate.c | 5 ----- > 2 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/target/riscv/internals.h b/target/riscv/internals.h > index 213aff31d8..4570bd50be 100644 > --- a/target/riscv/internals.h > +++ b/target/riscv/internals.h > @@ -201,4 +201,9 @@ static inline target_ulong adjust_addr_virt(CPURISCVState *env, > return adjust_addr_body(env, addr, true); > } > > +static inline int insn_len(uint16_t first_word) > +{ > + return (first_word & 3) == 3 ? 4 : 2; > +} > + > #endif > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index cef61b5b29..9836ab8c20 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -1210,11 +1210,6 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) > /* The specification allows for longer insns, but not supported by qemu. */ > #define MAX_INSN_LEN 4 > > -static inline int insn_len(uint16_t first_word) > -{ > - return (first_word & 3) == 3 ? 4 : 2; > -} > - > const RISCVDecoder decoder_table[] = { > { always_true_p, decode_insn32 }, > { has_xthead_p, decode_xthead}, > -- > 2.43.0 > >
diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 213aff31d8..4570bd50be 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -201,4 +201,9 @@ static inline target_ulong adjust_addr_virt(CPURISCVState *env, return adjust_addr_body(env, addr, true); } +static inline int insn_len(uint16_t first_word) +{ + return (first_word & 3) == 3 ? 4 : 2; +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index cef61b5b29..9836ab8c20 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1210,11 +1210,6 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) /* The specification allows for longer insns, but not supported by qemu. */ #define MAX_INSN_LEN 4 -static inline int insn_len(uint16_t first_word) -{ - return (first_word & 3) == 3 ? 4 : 2; -} - const RISCVDecoder decoder_table[] = { { always_true_p, decode_insn32 }, { has_xthead_p, decode_xthead},
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/internals.h | 5 +++++ target/riscv/translate.c | 5 ----- 2 files changed, 5 insertions(+), 5 deletions(-)