| Message ID | 20250418061500.1629200-4-shin.son@samsung.com |
|---|---|
| State | New |
| Headers | show |
| Series | add CPUCL0 clock support for exynosauto v920 SoC | expand |
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index fc6ac531d597..d1528633adfe 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -582,6 +582,21 @@ pinctrl_aud: pinctrl@1a460000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x1a460000 0x10000>; }; + + cmu_cpucl0: clock-controller@1ec00000 { + compatible = "samsung,exynosautov920-cmu-cpucl0"; + reg = <0x1EC00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_CPUCL0_SWITCH>, + <&cmu_top DOUT_CLKCMU_CPUCL0_CLUSTER>, + <&cmu_top DOUT_CLKCMU_CPUCL0_DBG>; + clock-names = "oscclk", + "switch", + "cluster", + "dbg"; + }; }; timer {
Add cmu_cpucl0 clocks for switch, cluster, and dbg domains respectively. Signed-off-by: Shin Son <shin.son@samsung.com> --- arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)