| Message ID | 20250417061245.497803-6-gokul.sriram.p@oss.qualcomm.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add new driver for WCSS secure PIL loading | expand |
On 4/17/25 8:12 AM, Gokul Sriram Palanisamy wrote: > Enable nodes required for q6 remoteproc bring up. > > Signed-off-by: Gokul Sriram Palanisamy <gokul.sriram.p@oss.qualcomm.com> > --- [...] > + apcs_glb: mailbox@f400004 { > + compatible = "qcom,ipq5424-apcs-apps-global", > + "qcom,ipq6018-apcs-apps-global"; > + reg = <0 0x0f400004 0 0x6000>; So either the offset in the driver is wrong, or the base here is wrong The IPC register is at 0x0f40000c + length is 0x10_000 [...]> + #clock-cells = <1>; > + #mbox-cells = <1>; > + }; > + > + tmel_qmp: qmp@32090000 { > + compatible = "qcom,ipq5424-tmel"; > + reg = <0 0x32090000 0 0x2000>; 0x4000-long, this should be much later on (sorted by unit address) > + interrupts = <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>; I'm not a 100% sure this is the right interrupt, but I'm not saying it's necessarily wrong The rest looks ok Konrad
On 4/26/2025 1:57 AM, Konrad Dybcio wrote: > On 4/17/25 8:12 AM, Gokul Sriram Palanisamy wrote: >> Enable nodes required for q6 remoteproc bring up. >> >> Signed-off-by: Gokul Sriram Palanisamy <gokul.sriram.p@oss.qualcomm.com> >> --- > [...] > >> + apcs_glb: mailbox@f400004 { >> + compatible = "qcom,ipq5424-apcs-apps-global", >> + "qcom,ipq6018-apcs-apps-global"; >> + reg = <0 0x0f400004 0 0x6000>; > So either the offset in the driver is wrong, or the base here > is wrong > > The IPC register is at 0x0f40000c > > + length is 0x10_000 with 0x0f400004, In apcs mailbox driver using offset as 8. Should I use 0x0f400000 with offset as 12 ? > > [...]> + #clock-cells = <1>; >> + #mbox-cells = <1>; >> + }; >> + >> + tmel_qmp: qmp@32090000 { >> + compatible = "qcom,ipq5424-tmel"; >> + reg = <0 0x32090000 0 0x2000>; > 0x4000-long, this should be much later on (sorted by unit address) ok, will update. >> + interrupts = <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>; > I'm not a 100% sure this is the right interrupt, but I'm not saying > it's necessarily wrong This is the interrupt being used and its validated and works fine. Regards, Gokul
On 5/5/25 3:47 PM, Gokul Sriram P wrote: > > On 4/26/2025 1:57 AM, Konrad Dybcio wrote: >> On 4/17/25 8:12 AM, Gokul Sriram Palanisamy wrote: >>> Enable nodes required for q6 remoteproc bring up. >>> >>> Signed-off-by: Gokul Sriram Palanisamy <gokul.sriram.p@oss.qualcomm.com> >>> --- >> [...] >> >>> + apcs_glb: mailbox@f400004 { >>> + compatible = "qcom,ipq5424-apcs-apps-global", >>> + "qcom,ipq6018-apcs-apps-global"; >>> + reg = <0 0x0f400004 0 0x6000>; >> So either the offset in the driver is wrong, or the base here >> is wrong >> >> The IPC register is at 0x0f40000c >> >> + length is 0x10_000 > > with 0x0f400004, In apcs mailbox driver using offset as 8. > > Should I use 0x0f400000 with offset as 12 ? Looks like, yes Konrad
diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 5d6ed2172b1b..ff43a969c511 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -3,7 +3,7 @@ * IPQ5424 device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -149,6 +149,11 @@ smem@8a800000 { hwlocks = <&tcsr_mutex 3>; }; + + q6_region: wcss@8a900000 { + reg = <0x0 0x8a900000 0x0 0x2800000>; + no-map; + }; }; soc@0 { @@ -541,6 +546,53 @@ dwc_0: usb@8a00000 { }; }; + apcs_glb: mailbox@f400004 { + compatible = "qcom,ipq5424-apcs-apps-global", + "qcom,ipq6018-apcs-apps-global"; + reg = <0 0x0f400004 0 0x6000>; + #clock-cells = <1>; + #mbox-cells = <1>; + }; + + tmel_qmp: qmp@32090000 { + compatible = "qcom,ipq5424-tmel"; + reg = <0 0x32090000 0 0x2000>; + interrupts = <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apcs_glb 20>; + #mbox-cells = <1>; + }; + + q6v5_wcss: remoteproc@d100000 { + compatible = "qcom,ipq5424-wcss-sec-pil"; + reg = <0 0x0d100000 0 0x4040>; + firmware-name = "ath12k/IPQ5424/hw1.0/q6_fw0.mbn"; + interrupts-extended = <&intc GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wcss_in 0 0>, + <&smp2p_wcss_in 1 0>, + <&smp2p_wcss_in 2 0>, + <&smp2p_wcss_in 3 0>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + mboxes = <&tmel_qmp 0>; + qcom,smem-states = <&smp2p_wcss_out 1>, + <&smp2p_wcss_out 0>; + qcom,smem-state-names = "stop", + "shutdown"; + + memory-region = <&q6_region>; + + glink-edge { + interrupts = <GIC_SPI 500 IRQ_TYPE_EDGE_RISING>; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + }; + timer@f420000 { compatible = "arm,armv7-timer-mem"; reg = <0 0xf420000 0 0x1000>; @@ -724,4 +776,28 @@ timer { <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; }; + + wcss: smp2p-wcss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs_glb 9>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_wcss_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_wcss_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; };
Enable nodes required for q6 remoteproc bring up. Signed-off-by: Gokul Sriram Palanisamy <gokul.sriram.p@oss.qualcomm.com> --- changes since v3: - added necessary padding for 8digt hex address in dts - fixed firmware-name to use .mbn format arch/arm64/boot/dts/qcom/ipq5424.dtsi | 78 ++++++++++++++++++++++++++- 1 file changed, 77 insertions(+), 1 deletion(-)