[01/21,arm] Separte tuning flags from architectural flags in CPU tables.

Message ID	3d879426-8667-e8ef-f575-9e1357c15736@arm.com
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of gcc-patches-return-444515-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; q=dns; s=default; b=gTFJVdYaoG5RAOt+ce9XMZCeyrjsh yYTTi8LLr/PDGIzRcLkgqphtZ8/BYAd8HxTTF291MdFGUR2D3OAunc2+E5H8hLix OtNTwSyyhPkR/X7lki/LAttjNqOvtKnujih1m1ejXYZix8u8AE0IPlCaUVTrtZcE RvrYtwokif2ZJg= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org From: "Richard Earnshaw (lists)" <Richard.Earnshaw@arm.com> Subject: [PATCH 01/21] [arm] Separte tuning flags from architectural flags in CPU tables. To: gcc-patches@gcc.gnu.org References: <cover.1481814793.git.Richard.Earnshaw@arm.com> Message-ID: <3d879426-8667-e8ef-f575-9e1357c15736@arm.com> Date: Thu, 15 Dec 2016 16:05:11 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <cover.1481814793.git.Richard.Earnshaw@arm.com> Content-Type: multipart/mixed; boundary="------------15E21DAF9BBA9CB8DD6F3A18"

diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c index c0de5d2..93a13c8 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -107,12 +107,12 @@ struct arm_arch_core_flag static const struct arm_arch_core_flag arm_arch_core_flags[] = { #undef ARM_CORE -#define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \ +#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) \ {NAME, FLAGS}, #include "config/arm/arm-cores.def" #undef ARM_CORE #undef ARM_ARCH -#define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \ +#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, FLAGS) \ {NAME, FLAGS}, #include "config/arm/arm-arches.def" #undef ARM_ARCH diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def index 71cabcc..d81a471 100644 --- a/gcc/config/arm/arm-arches.def +++ b/gcc/config/arm/arm-arches.def @@ -19,7 +19,7 @@ /* Before using #include to read this file, define a macro: - ARM_ARCH(NAME, CORE, ARCH, FLAGS) + ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, FLAGS) The NAME is the name of the architecture, represented as a string constant. The CORE is the identifier for a core representative of @@ -28,52 +28,41 @@ genopt.sh assumes no whitespace up to the first "," in each entry. */ -ARM_ARCH("armv2", arm2, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2)) -ARM_ARCH("armv2a", arm2, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2)) -ARM_ARCH("armv3", arm6, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3)) -ARM_ARCH("armv3m", arm7m, 3M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M)) -ARM_ARCH("armv4", arm7tdmi, 4, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4)) +ARM_ARCH("armv2", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2)) +ARM_ARCH("armv2a", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2)) +ARM_ARCH("armv3", arm6, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3)) +ARM_ARCH("armv3m", arm7m, TF_CO_PROC, 3M, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M)) +ARM_ARCH("armv4", arm7tdmi, TF_CO_PROC, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4)) /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no implementations that support it, so we will leave it out for now. */ -ARM_ARCH("armv4t", arm7tdmi, 4T, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH4T)) -ARM_ARCH("armv5", arm10tdmi, 5, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH5)) -ARM_ARCH("armv5t", arm10tdmi, 5T, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH5T)) -ARM_ARCH("armv5e", arm1026ejs, 5E, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH5E)) -ARM_ARCH("armv5te", arm1026ejs, 5TE, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH5TE)) -ARM_ARCH("armv6", arm1136js, 6, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6)) -ARM_ARCH("armv6j", arm1136js, 6J, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6J)) -ARM_ARCH("armv6k", mpcore, 6K, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6K)) -ARM_ARCH("armv6z", arm1176jzs, 6Z, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6Z)) -ARM_ARCH("armv6kz", arm1176jzs, 6KZ, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6KZ)) -ARM_ARCH("armv6zk", arm1176jzs, 6KZ, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6KZ)) -ARM_ARCH("armv6t2", arm1156t2s, 6T2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6T2)) -ARM_ARCH("armv6-m", cortexm1, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M)) -ARM_ARCH("armv6s-m", cortexm1, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M)) -ARM_ARCH("armv7", cortexa8, 7, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7)) -ARM_ARCH("armv7-a", cortexa8, 7A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7A)) -ARM_ARCH("armv7ve", cortexa8, 7A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7VE)) -ARM_ARCH("armv7-r", cortexr4, 7R, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7R)) -ARM_ARCH("armv7-m", cortexm3, 7M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7M)) -ARM_ARCH("armv7e-m", cortexm4, 7EM, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7EM)) -ARM_ARCH("armv8-a", cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH8A)) -ARM_ARCH("armv8-a+crc",cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A)) -ARM_ARCH("armv8.1-a", cortexa53, 8A, - ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A, - FL2_FOR_ARCH8_1A)) -ARM_ARCH("armv8.1-a+crc",cortexa53, 8A, - ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A, - FL2_FOR_ARCH8_1A)) -ARM_ARCH ("armv8.2-a", cortexa53, 8A, - ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A, - FL2_FOR_ARCH8_2A)) -ARM_ARCH ("armv8.2-a+fp16", cortexa53, 8A, - ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A, - FL2_FOR_ARCH8_2A | FL2_FP16INST)) -ARM_ARCH("armv8-m.base", cortexm23, 8M_BASE, - ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE)) -ARM_ARCH("armv8-m.main", cortexm7, 8M_MAIN, - ARM_FSET_MAKE (FL_CO_PROC | FL_FOR_ARCH8M_MAIN, FL2_CMSE)) -ARM_ARCH("armv8-m.main+dsp", cortexm33, 8M_MAIN, - ARM_FSET_MAKE (FL_CO_PROC | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE)) -ARM_ARCH("iwmmxt", iwmmxt, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT)) -ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2)) +ARM_ARCH("armv4t", arm7tdmi, TF_CO_PROC, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T)) +ARM_ARCH("armv5", arm10tdmi, TF_CO_PROC, 5, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5)) +ARM_ARCH("armv5t", arm10tdmi, TF_CO_PROC, 5T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T)) +ARM_ARCH("armv5e", arm1026ejs, TF_CO_PROC, 5E, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5E)) +ARM_ARCH("armv5te", arm1026ejs, TF_CO_PROC, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE)) +ARM_ARCH("armv6", arm1136js, TF_CO_PROC, 6, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6)) +ARM_ARCH("armv6j", arm1136js, TF_CO_PROC, 6J, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J)) +ARM_ARCH("armv6k", mpcore, TF_CO_PROC, 6K, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K)) +ARM_ARCH("armv6z", arm1176jzs, TF_CO_PROC, 6Z, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6Z)) +ARM_ARCH("armv6kz", arm1176jzs, TF_CO_PROC, 6KZ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ)) +ARM_ARCH("armv6zk", arm1176jzs, TF_CO_PROC, 6KZ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ)) +ARM_ARCH("armv6t2", arm1156t2s, TF_CO_PROC, 6T2, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2)) +ARM_ARCH("armv6-m", cortexm1, 0, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M)) +ARM_ARCH("armv6s-m", cortexm1, 0, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M)) +ARM_ARCH("armv7", cortexa8, TF_CO_PROC, 7, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7)) +ARM_ARCH("armv7-a", cortexa8, TF_CO_PROC, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A)) +ARM_ARCH("armv7ve", cortexa8, TF_CO_PROC, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7VE)) +ARM_ARCH("armv7-r", cortexr4, TF_CO_PROC, 7R, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R)) +ARM_ARCH("armv7-m", cortexm3, TF_CO_PROC, 7M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M)) +ARM_ARCH("armv7e-m", cortexm4, TF_CO_PROC, 7EM, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM)) +ARM_ARCH("armv8-a", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A)) +ARM_ARCH("armv8-a+crc",cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A)) +ARM_ARCH("armv8.1-a", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A)) +ARM_ARCH("armv8.1-a+crc",cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A)) +ARM_ARCH ("armv8.2-a", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A)) +ARM_ARCH ("armv8.2-a+fp16", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A | FL2_FP16INST)) +ARM_ARCH("armv8-m.base", cortexm23, 0, 8M_BASE, ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE)) +ARM_ARCH("armv8-m.main", cortexm7, TF_CO_PROC, 8M_MAIN, ARM_FSET_MAKE (FL_FOR_ARCH8M_MAIN, FL2_CMSE)) +ARM_ARCH("armv8-m.main+dsp", cortexm33, TF_CO_PROC, 8M_MAIN, ARM_FSET_MAKE (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE)) +ARM_ARCH("iwmmxt", iwmmxt, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT)) +ARM_ARCH("iwmmxt2", iwmmxt2, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2)) diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index fd96a41..27b156a 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -25,13 +25,14 @@ /* Before using #include to read this file, define a macro: - ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, ARCH, FLAGS, COSTS) + ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) The CORE_NAME is the name of the core, represented as a string constant. The INTERNAL_IDENT is the name of the core represented as an identifier. This must be unique for each entry in this table. The TUNE_IDENT is the name of the core for which scheduling decisions should be made, represented as an identifier. + TUNE_FLAGS is a set of flag bits that are used to affect tuning. ARCH is the architecture revision implemented by the chip. FLAGS is the set of feature flags of that core. This need not include flags implied by the architecture. @@ -43,145 +44,144 @@ Some tools assume no whitespace up to the first "," in each entry. */ /* V2/V2A Architecture Processors */ -ARM_CORE("arm2", arm2, arm2, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2), slowmul) -ARM_CORE("arm250", arm250, arm250, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2), slowmul) -ARM_CORE("arm3", arm3, arm3, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2), slowmul) +ARM_CORE("arm2", arm2, arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul) +ARM_CORE("arm250", arm250, arm250, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul) +ARM_CORE("arm3", arm3, arm3, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul) /* V3 Architecture Processors */ -ARM_CORE("arm6", arm6, arm6, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul) -ARM_CORE("arm60", arm60, arm60, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul) -ARM_CORE("arm600", arm600, arm600, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) -ARM_CORE("arm610", arm610, arm610, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) -ARM_CORE("arm620", arm620, arm620, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) -ARM_CORE("arm7", arm7, arm7, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul) -ARM_CORE("arm7d", arm7d, arm7d, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul) -ARM_CORE("arm7di", arm7di, arm7di, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul) -ARM_CORE("arm70", arm70, arm70, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul) -ARM_CORE("arm700", arm700, arm700, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) -ARM_CORE("arm700i", arm700i, arm700i, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) -ARM_CORE("arm710", arm710, arm710, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) -ARM_CORE("arm720", arm720, arm720, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) -ARM_CORE("arm710c", arm710c, arm710c, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) -ARM_CORE("arm7100", arm7100, arm7100, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) -ARM_CORE("arm7500", arm7500, arm7500, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm6", arm6, arm6, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm60", arm60, arm60, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm600", arm600, arm600, (TF_CO_PROC | TF_WBUF), 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm610", arm610, arm610, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm620", arm620, arm620, (TF_CO_PROC | TF_WBUF), 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm7", arm7, arm7, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm7d", arm7d, arm7d, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm7di", arm7di, arm7di, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm70", arm70, arm70, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm700", arm700, arm700, (TF_CO_PROC | TF_WBUF), 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm700i", arm700i, arm700i, (TF_CO_PROC | TF_WBUF), 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm710", arm710, arm710, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm720", arm720, arm720, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm710c", arm710c, arm710c, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm7100", arm7100, arm7100, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm7500", arm7500, arm7500, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) /* Doesn't have an external co-proc, but does have embedded fpa. */ -ARM_CORE("arm7500fe", arm7500fe, arm7500fe, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm7500fe", arm7500fe, arm7500fe, (TF_CO_PROC | TF_WBUF), 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul) /* V3M Architecture Processors */ /* arm7m doesn't exist on its own, but only with D, ("and", and I), but those don't alter the code, so arm7m is sometimes used. */ -ARM_CORE("arm7m", arm7m, arm7m, 3M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M), fastmul) -ARM_CORE("arm7dm", arm7dm, arm7dm, 3M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M), fastmul) -ARM_CORE("arm7dmi", arm7dmi, arm7dmi, 3M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M), fastmul) +ARM_CORE("arm7m", arm7m, arm7m, TF_CO_PROC, 3M, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul) +ARM_CORE("arm7dm", arm7dm, arm7dm, TF_CO_PROC, 3M, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul) +ARM_CORE("arm7dmi", arm7dmi, arm7dmi, TF_CO_PROC, 3M, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul) /* V4 Architecture Processors */ -ARM_CORE("arm8", arm8, arm8, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4), fastmul) -ARM_CORE("arm810", arm810, arm810, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4), fastmul) -ARM_CORE("strongarm", strongarm, strongarm, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm) -ARM_CORE("strongarm110", strongarm110, strongarm110, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm) -ARM_CORE("strongarm1100", strongarm1100, strongarm1100, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm) -ARM_CORE("strongarm1110", strongarm1110, strongarm1110, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm) -ARM_CORE("fa526", fa526, fa526, 4, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4), fastmul) -ARM_CORE("fa626", fa626, fa626, 4, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4), fastmul) +ARM_CORE("arm8", arm8, arm8, TF_LDSCHED, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul) +ARM_CORE("arm810", arm810, arm810, TF_LDSCHED, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul) +ARM_CORE("strongarm", strongarm, strongarm, (TF_LDSCHED | TF_STRONG), 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm) +ARM_CORE("strongarm110", strongarm110, strongarm110, (TF_LDSCHED | TF_STRONG), 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm) +ARM_CORE("strongarm1100", strongarm1100, strongarm1100, (TF_LDSCHED | TF_STRONG), 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm) +ARM_CORE("strongarm1110", strongarm1110, strongarm1110, (TF_LDSCHED | TF_STRONG), 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm) +ARM_CORE("fa526", fa526, fa526, TF_LDSCHED, 4, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul) +ARM_CORE("fa626", fa626, fa626, TF_LDSCHED, 4, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul) /* V4T Architecture Processors */ -ARM_CORE("arm7tdmi", arm7tdmi, arm7tdmi, 4T, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH4T), fastmul) -ARM_CORE("arm7tdmi-s", arm7tdmis, arm7tdmis, 4T, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH4T), fastmul) -ARM_CORE("arm710t", arm710t, arm710t, 4T, ARM_FSET_MAKE_CPU1 (FL_WBUF | FL_FOR_ARCH4T), fastmul) -ARM_CORE("arm720t", arm720t, arm720t, 4T, ARM_FSET_MAKE_CPU1 (FL_WBUF | FL_FOR_ARCH4T), fastmul) -ARM_CORE("arm740t", arm740t, arm740t, 4T, ARM_FSET_MAKE_CPU1 (FL_WBUF | FL_FOR_ARCH4T), fastmul) -ARM_CORE("arm9", arm9, arm9, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul) -ARM_CORE("arm9tdmi", arm9tdmi, arm9tdmi, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul) -ARM_CORE("arm920", arm920, arm920, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul) -ARM_CORE("arm920t", arm920t, arm920t, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul) -ARM_CORE("arm922t", arm922t, arm922t, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul) -ARM_CORE("arm940t", arm940t, arm940t, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul) -ARM_CORE("ep9312", ep9312, ep9312, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm7tdmi", arm7tdmi, arm7tdmi, TF_CO_PROC, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm7tdmi-s", arm7tdmis, arm7tdmis, TF_CO_PROC, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm710t", arm710t, arm710t, TF_WBUF, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm720t", arm720t, arm720t, TF_WBUF, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm740t", arm740t, arm740t, TF_WBUF, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm9", arm9, arm9, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm9tdmi", arm9tdmi, arm9tdmi, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm920", arm920, arm920, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm920t", arm920t, arm920t, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm922t", arm922t, arm922t, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm940t", arm940t, arm940t, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul) +ARM_CORE("ep9312", ep9312, ep9312, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul) /* V5T Architecture Processors */ -ARM_CORE("arm10tdmi", arm10tdmi, arm10tdmi, 5T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5T), fastmul) -ARM_CORE("arm1020t", arm1020t, arm1020t, 5T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5T), fastmul) +ARM_CORE("arm10tdmi", arm10tdmi, arm10tdmi, TF_LDSCHED, 5T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul) +ARM_CORE("arm1020t", arm1020t, arm1020t, TF_LDSCHED, 5T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul) /* V5TE Architecture Processors */ -ARM_CORE("arm9e", arm9e, arm9e, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e) -ARM_CORE("arm946e-s", arm946es, arm946es, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e) -ARM_CORE("arm966e-s", arm966es, arm966es, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e) -ARM_CORE("arm968e-s", arm968es, arm968es, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e) -ARM_CORE("arm10e", arm10e, arm10e, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fastmul) -ARM_CORE("arm1020e", arm1020e, arm1020e, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fastmul) -ARM_CORE("arm1022e", arm1022e, arm1022e, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fastmul) -ARM_CORE("xscale", xscale, xscale, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_FOR_ARCH5TE), xscale) -ARM_CORE("iwmmxt", iwmmxt, iwmmxt, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE), xscale) -ARM_CORE("iwmmxt2", iwmmxt2, iwmmxt2, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE), xscale) -ARM_CORE("fa606te", fa606te, fa606te, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e) -ARM_CORE("fa626te", fa626te, fa626te, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e) -ARM_CORE("fmp626", fmp626, fmp626, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e) -ARM_CORE("fa726te", fa726te, fa726te, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fa726te) +ARM_CORE("arm9e", arm9e, arm9e, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e) +ARM_CORE("arm946e-s", arm946es, arm946es, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e) +ARM_CORE("arm966e-s", arm966es, arm966es, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e) +ARM_CORE("arm968e-s", arm968es, arm968es, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e) +ARM_CORE("arm10e", arm10e, arm10e, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul) +ARM_CORE("arm1020e", arm1020e, arm1020e, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul) +ARM_CORE("arm1022e", arm1022e, arm1022e, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul) +ARM_CORE("xscale", xscale, xscale, (TF_LDSCHED | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_FOR_ARCH5TE), xscale) +ARM_CORE("iwmmxt", iwmmxt, iwmmxt, (TF_LDSCHED | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE), xscale) +ARM_CORE("iwmmxt2", iwmmxt2, iwmmxt2, (TF_LDSCHED | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE), xscale) +ARM_CORE("fa606te", fa606te, fa606te, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e) +ARM_CORE("fa626te", fa626te, fa626te, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e) +ARM_CORE("fmp626", fmp626, fmp626, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e) +ARM_CORE("fa726te", fa726te, fa726te, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fa726te) /* V5TEJ Architecture Processors */ -ARM_CORE("arm926ej-s", arm926ejs, arm926ejs, 5TEJ, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TEJ), 9e) -ARM_CORE("arm1026ej-s", arm1026ejs, arm1026ejs, 5TEJ, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TEJ), 9e) +ARM_CORE("arm926ej-s", arm926ejs, arm926ejs, TF_LDSCHED, 5TEJ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e) +ARM_CORE("arm1026ej-s", arm1026ejs, arm1026ejs, TF_LDSCHED, 5TEJ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e) /* V6 Architecture Processors */ -ARM_CORE("arm1136j-s", arm1136js, arm1136js, 6J, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6J), 9e) -ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, 6J, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6J), 9e) -ARM_CORE("arm1176jz-s", arm1176jzs, arm1176jzs, 6KZ, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6KZ), 9e) -ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, 6KZ, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6KZ), 9e) -ARM_CORE("mpcorenovfp", mpcorenovfp, mpcorenovfp, 6K, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6K), 9e) -ARM_CORE("mpcore", mpcore, mpcore, 6K, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6K), 9e) -ARM_CORE("arm1156t2-s", arm1156t2s, arm1156t2s, 6T2, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6T2), v6t2) -ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, 6T2, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6T2), v6t2) +ARM_CORE("arm1136j-s", arm1136js, arm1136js, TF_LDSCHED, 6J, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J), 9e) +ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, TF_LDSCHED, 6J, ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6J), 9e) +ARM_CORE("arm1176jz-s", arm1176jzs, arm1176jzs, TF_LDSCHED, 6KZ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ), 9e) +ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, TF_LDSCHED, 6KZ, ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6KZ), 9e) +ARM_CORE("mpcorenovfp", mpcorenovfp, mpcorenovfp, TF_LDSCHED, 6K, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K), 9e) +ARM_CORE("mpcore", mpcore, mpcore, TF_LDSCHED, 6K, ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6K), 9e) +ARM_CORE("arm1156t2-s", arm1156t2s, arm1156t2s, TF_LDSCHED, 6T2, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2), v6t2) +ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, TF_LDSCHED, 6T2, ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6T2), v6t2) /* V6M Architecture Processors */ -ARM_CORE("cortex-m1", cortexm1, cortexm1, 6M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6M), v6m) -ARM_CORE("cortex-m0", cortexm0, cortexm0, 6M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6M), v6m) -ARM_CORE("cortex-m0plus", cortexm0plus, cortexm0plus, 6M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6M), v6m) +ARM_CORE("cortex-m1", cortexm1, cortexm1, TF_LDSCHED, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m) +ARM_CORE("cortex-m0", cortexm0, cortexm0, TF_LDSCHED, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m) +ARM_CORE("cortex-m0plus", cortexm0plus, cortexm0plus, TF_LDSCHED, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m) /* V6M Architecture Processors for small-multiply implementations. */ -ARM_CORE("cortex-m1.small-multiply", cortexm1smallmultiply, cortexm1, 6M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M), v6m) -ARM_CORE("cortex-m0.small-multiply", cortexm0smallmultiply, cortexm0, 6M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M), v6m) -ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus,6M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M), v6m) +ARM_CORE("cortex-m1.small-multiply", cortexm1smallmultiply, cortexm1, (TF_LDSCHED | TF_SMALLMUL), 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m) +ARM_CORE("cortex-m0.small-multiply", cortexm0smallmultiply, cortexm0, (TF_LDSCHED | TF_SMALLMUL), 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m) +ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus, (TF_LDSCHED | TF_SMALLMUL), 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m) /* V7 Architecture Processors */ -ARM_CORE("generic-armv7-a", genericv7a, genericv7a, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex) -ARM_CORE("cortex-a5", cortexa5, cortexa5, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a5) -ARM_CORE("cortex-a7", cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7) -ARM_CORE("cortex-a8", cortexa8, cortexa8, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a8) -ARM_CORE("cortex-a9", cortexa9, cortexa9, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a9) -ARM_CORE("cortex-a12", cortexa12, cortexa17, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) -ARM_CORE("cortex-a15", cortexa15, cortexa15, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15) -ARM_CORE("cortex-a17", cortexa17, cortexa17, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) -ARM_CORE("cortex-r4", cortexr4, cortexr4, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7R), cortex) -ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7R), cortex) -ARM_CORE("cortex-r5", cortexr5, cortexr5, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex) -ARM_CORE("cortex-r7", cortexr7, cortexr7, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex) -ARM_CORE("cortex-r8", cortexr8, cortexr7, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex) -ARM_CORE("cortex-m7", cortexm7, cortexm7, 7EM, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7) -ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7EM), v7m) -ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7M), v7m) -ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), marvell_pj4) +ARM_CORE("generic-armv7-a", genericv7a, genericv7a, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex) +ARM_CORE("cortex-a5", cortexa5, cortexa5, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a5) +ARM_CORE("cortex-a7", cortexa7, cortexa7, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7) +ARM_CORE("cortex-a8", cortexa8, cortexa8, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a8) +ARM_CORE("cortex-a9", cortexa9, cortexa9, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a9) +ARM_CORE("cortex-a12", cortexa12, cortexa17, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) +ARM_CORE("cortex-a15", cortexa15, cortexa15, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15) +ARM_CORE("cortex-a17", cortexa17, cortexa17, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) +ARM_CORE("cortex-r4", cortexr4, cortexr4, TF_LDSCHED, 7R, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex) +ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, TF_LDSCHED, 7R, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex) +ARM_CORE("cortex-r5", cortexr5, cortexr5, TF_LDSCHED, 7R, ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex) +ARM_CORE("cortex-r7", cortexr7, cortexr7, TF_LDSCHED, 7R, ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex) +ARM_CORE("cortex-r8", cortexr8, cortexr7, TF_LDSCHED, 7R, ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex) +ARM_CORE("cortex-m7", cortexm7, cortexm7, TF_LDSCHED, 7EM, ARM_FSET_MAKE_CPU1 (FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7) +ARM_CORE("cortex-m4", cortexm4, cortexm4, TF_LDSCHED, 7EM, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM), v7m) +ARM_CORE("cortex-m3", cortexm3, cortexm3, TF_LDSCHED, 7M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m) +ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), marvell_pj4) /* V7 big.LITTLE implementations */ -ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15) -ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) +ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15) +ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) /* V8 Architecture Processors */ -ARM_CORE("cortex-a32", cortexa32, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35) -ARM_CORE("cortex-a35", cortexa35, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35) -ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53) -ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) -ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) -ARM_CORE("cortex-a73", cortexa73, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73) -ARM_CORE("cortex-m23", cortexm23, cortexm23, 8M_BASE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8M_BASE), v6m) -ARM_CORE("cortex-m33", cortexm33, cortexm33, 8M_MAIN, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m) -ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), exynosm1) -ARM_CORE("falkor", falkor, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx) -ARM_CORE("qdf24xx", qdf24xx, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx) -ARM_CORE("xgene1", xgene1, xgene1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A), xgene1) +ARM_CORE("cortex-a32", cortexa32, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35) +ARM_CORE("cortex-a35", cortexa35, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35) +ARM_CORE("cortex-a53", cortexa53, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a53) +ARM_CORE("cortex-a57", cortexa57, cortexa57, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) +ARM_CORE("cortex-a72", cortexa72, cortexa57, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) +ARM_CORE("cortex-a73", cortexa73, cortexa57, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73) +ARM_CORE("cortex-m23", cortexm23, cortexm23, TF_LDSCHED, 8M_BASE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8M_BASE), v6m) +ARM_CORE("cortex-m33", cortexm33, cortexm33, TF_LDSCHED, 8M_MAIN, ARM_FSET_MAKE_CPU1 (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m) +ARM_CORE("exynos-m1", exynosm1, exynosm1, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), exynosm1) +ARM_CORE("falkor", falkor, cortexa57, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx) +ARM_CORE("qdf24xx", qdf24xx, cortexa57, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx) +ARM_CORE("xgene1", xgene1, xgene1, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A), xgene1) /* V8 big.LITTLE implementations */ -ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) -ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) -ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73) -ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73) - +ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) +ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) +ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73) +ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73) diff --git a/gcc/config/arm/arm-flags.h b/gcc/config/arm/arm-flags.h index fb49838..6482c64 100644 --- a/gcc/config/arm/arm-flags.h +++ b/gcc/config/arm/arm-flags.h @@ -22,6 +22,16 @@ #ifndef GCC_ARM_FLAGS_H #define GCC_ARM_FLAGS_H +/* Flags used to identify a few tuning properties. These are for legacy + purposes only. Do not add any more of these: use the main tuning tables. */ +#define TF_LDSCHED (1U << 0) +#define TF_WBUF (1U << 1) +#define TF_CO_PROC (1U << 2) +#define TF_SMALLMUL (1U << 3) +#define TF_STRONG (1U << 4) +#define TF_XSCALE (1U << 5) +#define TF_NO_MODE32 (1U << 6) + /* Flags used to identify the presence of processor capabilities. */ /* Bit values used to identify processor capabilities. */ @@ -34,16 +44,15 @@ #define FL_ARCH4 (1U << 4) /* Architecture rel 4. */ #define FL_ARCH5 (1U << 5) /* Architecture rel 5. */ #define FL_THUMB (1U << 6) /* Thumb aware. */ -#define FL_LDSCHED (1U << 7) /* Load scheduling necessary. */ -#define FL_STRONG (1U << 8) /* StrongARM. */ +/* Spare (1U << 7) */ +/* Spare (1U << 8) */ #define FL_ARCH5E (1U << 9) /* DSP extensions to v5. */ #define FL_XSCALE (1U << 10) /* XScale. */ -/* spare (1U << 11) */ +/* Spare (1U << 11) */ #define FL_ARCH6 (1U << 12) /* Architecture rel 6. Adds media instructions. */ #define FL_VFPV2 (1U << 13) /* Vector Floating Point V2. */ -#define FL_WBUF (1U << 14) /* Schedule for write buffer ops. - Note: ARM6 & 7 derivatives only. */ +/* Spare (1U << 14) */ #define FL_ARCH6K (1U << 15) /* Architecture rel 6 K extensions. */ #define FL_THUMB2 (1U << 16) /* Thumb-2. */ #define FL_NOTM (1U << 17) /* Instructions not present in the 'M' @@ -57,7 +66,7 @@ #define FL_ARM_DIV (1U << 23) /* Hardware divide (ARM mode). */ #define FL_ARCH8 (1U << 24) /* Architecture 8. */ #define FL_CRC32 (1U << 25) /* ARMv8 CRC32 instructions. */ -#define FL_SMALLMUL (1U << 26) /* Small multiply supported. */ +/* Spare (1U << 26) */ #define FL_NO_VOLATILE_CE (1U << 27) /* No volatile memory in IT block. */ #define FL_IWMMXT (1U << 29) /* XScale v2 or "Intel Wireless MMX @@ -73,8 +82,7 @@ #define FL2_CMSE (1U << 3) /* ARMv8-M Security Extensions. */ /* Flags that only effect tuning, not available instructions. */ -#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \ - | FL_CO_PROC) +#define FL_TUNE (FL_VFPV2) #define FL_FOR_ARCH2 FL_NOTM #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32) diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h index e06fedb..6f15065 100644 --- a/gcc/config/arm/arm-opts.h +++ b/gcc/config/arm/arm-opts.h @@ -31,7 +31,7 @@ enum processor_type { #undef ARM_CORE -#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \ +#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) \ TARGET_CPU_##INTERNAL_IDENT, #include "arm-cores.def" #undef ARM_CORE diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 05d73ab..2ec9a4e3 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -358,7 +358,7 @@ extern arm_feature_set insn_flags; /* The bits in this mask specify which instruction scheduling options should be used. */ -extern arm_feature_set tune_flags; +extern unsigned int tune_flags; /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ extern int arm_arch3m; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 437da6f..2caaba4 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -785,7 +785,7 @@ arm_feature_set insn_flags = ARM_FSET_EMPTY; /* The bits in this mask specify which instruction scheduling options should be used. */ -arm_feature_set tune_flags = ARM_FSET_EMPTY; +unsigned int tune_flags = 0; /* The highest ARM architecture version supported by the target. */ @@ -950,6 +950,7 @@ struct processors { const char *const name; enum processor_type core; + unsigned int tune_flags; const char *arch; enum base_architecture base_arch; const arm_feature_set flags; @@ -2287,12 +2288,12 @@ const struct tune_params arm_fa726te_tune = static const struct processors all_cores[] = { /* ARM Cores */ -#define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \ - {NAME, TARGET_CPU_##IDENT, #ARCH, BASE_ARCH_##ARCH, \ +#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) \ + {NAME, TARGET_CPU_##IDENT, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, \ FLAGS, &arm_##COSTS##_tune}, #include "arm-cores.def" #undef ARM_CORE - {NULL, TARGET_CPU_arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL} + {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL} }; static const struct processors all_architectures[] = @@ -2301,11 +2302,11 @@ static const struct processors all_architectures[] = /* We don't specify tuning costs here as it will be figured out from the core. */ -#define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \ - {NAME, TARGET_CPU_##CORE, #ARCH, BASE_ARCH_##ARCH, FLAGS, NULL}, +#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, FLAGS) \ + {NAME, TARGET_CPU_##CORE, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, FLAGS, NULL}, #include "arm-arches.def" #undef ARM_ARCH - {NULL, TARGET_CPU_arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL} + {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL} }; @@ -3177,7 +3178,7 @@ arm_option_override (void) arm_base_arch = arm_selected_cpu->base_arch; arm_tune = arm_selected_tune->core; - tune_flags = arm_selected_tune->flags; + tune_flags = arm_selected_tune->tune_flags; current_tune = arm_selected_tune->tune; /* TBD: Dwarf info for apcs frame is not handled yet. */ @@ -3228,10 +3229,10 @@ arm_option_override (void) arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2); arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE); - arm_ld_sched = ARM_FSET_HAS_CPU1 (tune_flags, FL_LDSCHED); - arm_tune_strongarm = ARM_FSET_HAS_CPU1 (tune_flags, FL_STRONG); - arm_tune_wbuf = ARM_FSET_HAS_CPU1 (tune_flags, FL_WBUF); - arm_tune_xscale = ARM_FSET_HAS_CPU1 (tune_flags, FL_XSCALE); + arm_ld_sched = (tune_flags & TF_LDSCHED) != 0; + arm_tune_strongarm = (tune_flags & TF_STRONG) != 0; + arm_tune_wbuf = (tune_flags & TF_WBUF) != 0; + arm_tune_xscale = (tune_flags & TF_XSCALE) != 0; arm_arch_iwmmxt = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT); arm_arch_iwmmxt2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT2); arm_arch_thumb_hwdiv = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB_DIV); @@ -3240,7 +3241,7 @@ arm_option_override (void) arm_tune_cortex_a9 = (arm_tune == TARGET_CPU_cortexa9) != 0; arm_arch_crc = ARM_FSET_HAS_CPU1 (insn_flags, FL_CRC32); arm_arch_cmse = ARM_FSET_HAS_CPU2 (insn_flags, FL2_CMSE); - arm_m_profile_small_mul = ARM_FSET_HAS_CPU1 (insn_flags, FL_SMALLMUL); + arm_m_profile_small_mul = (tune_flags & TF_SMALLMUL) != 0; arm_fp16_inst = ARM_FSET_HAS_CPU2 (insn_flags, FL2_FP16INST); if (arm_fp16_inst) { @@ -3324,7 +3325,7 @@ arm_option_override (void) /* For arm2/3 there is no need to do any scheduling if we are doing software floating-point. */ - if (TARGET_SOFT_FLOAT && !ARM_FSET_HAS_CPU1 (tune_flags, FL_MODE32)) + if (TARGET_SOFT_FLOAT && (tune_flags & TF_NO_MODE32)) flag_schedule_insns = flag_schedule_insns_after_reload = 0; /* Use the cp15 method if it is available. */

[01/21,arm] Separte tuning flags from architectural flags in CPU tables.

Commit Message

Patch