diff mbox series

[v4,090/163] tcg: Merge INDEX_op_bswap32_{i32,i64}

Message ID 20250415192515.232910-91-richard.henderson@linaro.org
State New
Headers show
Series tcg: Convert to TCGOutOp structures | expand

Commit Message

Richard Henderson April 15, 2025, 7:24 p.m. UTC 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg-opc.h    |  4 +---
 tcg/optimize.c           |  7 +++----
 tcg/tcg-op.c             |  8 ++++----
 tcg/tcg.c                |  9 +++------
 tcg/tci.c                |  5 ++---
 docs/devel/tcg-ops.rst   | 13 ++++++-------
 tcg/tci/tcg-target.c.inc |  2 +-
 7 files changed, 20 insertions(+), 28 deletions(-)

Comments

Pierrick Bouvier April 15, 2025, 9:47 p.m. UTC | #1 
On 4/15/25 12:24, Richard Henderson wrote:
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   include/tcg/tcg-opc.h    |  4 +---
>   tcg/optimize.c           |  7 +++----
>   tcg/tcg-op.c             |  8 ++++----
>   tcg/tcg.c                |  9 +++------
>   tcg/tci.c                |  5 ++---
>   docs/devel/tcg-ops.rst   | 13 ++++++-------
>   tcg/tci/tcg-target.c.inc |  2 +-
>   7 files changed, 20 insertions(+), 28 deletions(-)
> 
> diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
> index acfbaa05b4..296dffe99a 100644
> --- a/include/tcg/tcg-opc.h
> +++ b/include/tcg/tcg-opc.h
> @@ -44,6 +44,7 @@ DEF(add, 1, 2, 0, TCG_OPF_INT)
>   DEF(and, 1, 2, 0, TCG_OPF_INT)
>   DEF(andc, 1, 2, 0, TCG_OPF_INT)
>   DEF(bswap16, 1, 1, 1, TCG_OPF_INT)
> +DEF(bswap32, 1, 1, 1, TCG_OPF_INT)
>   DEF(clz, 1, 2, 0, TCG_OPF_INT)
>   DEF(ctpop, 1, 1, 0, TCG_OPF_INT)
>   DEF(ctz, 1, 2, 0, TCG_OPF_INT)
> @@ -96,8 +97,6 @@ DEF(sub2_i32, 2, 4, 0, 0)
>   DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
>   DEF(setcond2_i32, 1, 4, 1, 0)
>   
> -DEF(bswap32_i32, 1, 1, 1, 0)
> -
>   /* load/store */
>   DEF(ld8u_i64, 1, 1, 1, 0)
>   DEF(ld8s_i64, 1, 1, 1, 0)
> @@ -122,7 +121,6 @@ DEF(extu_i32_i64, 1, 1, 0, 0)
>   DEF(extrl_i64_i32, 1, 1, 0, 0)
>   DEF(extrh_i64_i32, 1, 1, 0, 0)
>   
> -DEF(bswap32_i64, 1, 1, 1, 0)
>   DEF(bswap64_i64, 1, 1, 1, 0)
>   
>   DEF(add2_i64, 2, 4, 0, 0)
> diff --git a/tcg/optimize.c b/tcg/optimize.c
> index 75849a1495..be9d09467d 100644
> --- a/tcg/optimize.c
> +++ b/tcg/optimize.c
> @@ -510,7 +510,7 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type,
>           x = bswap16(x);
>           return y & TCG_BSWAP_OS ? (int16_t)x : x;
>   
> -    CASE_OP_32_64(bswap32):
> +    case INDEX_op_bswap32:
>           x = bswap32(x);
>           return y & TCG_BSWAP_OS ? (int32_t)x : x;
>   
> @@ -1564,8 +1564,7 @@ static bool fold_bswap(OptContext *ctx, TCGOp *op)
>           z_mask = bswap16(z_mask);
>           sign = INT16_MIN;
>           break;
> -    case INDEX_op_bswap32_i32:
> -    case INDEX_op_bswap32_i64:
> +    case INDEX_op_bswap32:
>           z_mask = bswap32(z_mask);
>           sign = INT32_MIN;
>           break;
> @@ -2858,7 +2857,7 @@ void tcg_optimize(TCGContext *s)
>               done = fold_brcond2(&ctx, op);
>               break;
>           case INDEX_op_bswap16:
> -        CASE_OP_32_64(bswap32):
> +        case INDEX_op_bswap32:
>           case INDEX_op_bswap64_i64:
>               done = fold_bswap(&ctx, op);
>               break;
> diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
> index 68e53a9c85..b1174f60cc 100644
> --- a/tcg/tcg-op.c
> +++ b/tcg/tcg-op.c
> @@ -1294,8 +1294,8 @@ void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags)
>    */
>   void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
>   {
> -    if (tcg_op_supported(INDEX_op_bswap32_i32, TCG_TYPE_I32, 0)) {
> -        tcg_gen_op3i_i32(INDEX_op_bswap32_i32, ret, arg, 0);
> +    if (tcg_op_supported(INDEX_op_bswap32, TCG_TYPE_I32, 0)) {
> +        tcg_gen_op3i_i32(INDEX_op_bswap32, ret, arg, 0);
>       } else {
>           TCGv_i32 t0 = tcg_temp_ebb_new_i32();
>           TCGv_i32 t1 = tcg_temp_ebb_new_i32();
> @@ -2137,8 +2137,8 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags)
>           } else {
>               tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
>           }
> -    } else if (tcg_op_supported(INDEX_op_bswap32_i64, TCG_TYPE_I64, 0)) {
> -        tcg_gen_op3i_i64(INDEX_op_bswap32_i64, ret, arg, flags);
> +    } else if (tcg_op_supported(INDEX_op_bswap32, TCG_TYPE_I64, 0)) {
> +        tcg_gen_op3i_i64(INDEX_op_bswap32, ret, arg, flags);
>       } else {
>           TCGv_i64 t0 = tcg_temp_ebb_new_i64();
>           TCGv_i64 t1 = tcg_temp_ebb_new_i64();
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 117021f610..51f9cc7fe1 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -1076,8 +1076,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
>       OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
>       OUTOP(INDEX_op_brcond, TCGOutOpBrcond, outop_brcond),
>       OUTOP(INDEX_op_bswap16, TCGOutOpBswap, outop_bswap16),
> -    OUTOP(INDEX_op_bswap32_i32, TCGOutOpBswap, outop_bswap32),
> -    OUTOP(INDEX_op_bswap32_i64, TCGOutOpBswap, outop_bswap32),
> +    OUTOP(INDEX_op_bswap32, TCGOutOpBswap, outop_bswap32),
>       OUTOP(INDEX_op_clz, TCGOutOpBinary, outop_clz),
>       OUTOP(INDEX_op_ctpop, TCGOutOpUnary, outop_ctpop),
>       OUTOP(INDEX_op_ctz, TCGOutOpBinary, outop_ctz),
> @@ -2939,8 +2938,7 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs)
>                   }
>                   break;
>               case INDEX_op_bswap16:
> -            case INDEX_op_bswap32_i32:
> -            case INDEX_op_bswap32_i64:
> +            case INDEX_op_bswap32:
>               case INDEX_op_bswap64_i64:
>                   {
>                       TCGArg flags = op->args[k];
> @@ -5483,8 +5481,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
>           break;
>   
>       case INDEX_op_bswap16:
> -    case INDEX_op_bswap32_i32:
> -    case INDEX_op_bswap32_i64:
> +    case INDEX_op_bswap32:
>           {
>               const TCGOutOpBswap *out =
>                   container_of(all_outop[op->opc], TCGOutOpBswap, base);
> diff --git a/tcg/tci.c b/tcg/tci.c
> index 0cb89f3256..f98c437100 100644
> --- a/tcg/tci.c
> +++ b/tcg/tci.c
> @@ -690,7 +690,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
>               tci_args_rr(insn, &r0, &r1);
>               regs[r0] = bswap16(regs[r1]);
>               break;
> -        CASE_32_64(bswap32)
> +        case INDEX_op_bswap32:
>               tci_args_rr(insn, &r0, &r1);
>               regs[r0] = bswap32(regs[r1]);
>               break;
> @@ -1004,14 +1004,13 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
>           break;
>   
>       case INDEX_op_bswap16:
> +    case INDEX_op_bswap32:
>       case INDEX_op_ctpop:
>       case INDEX_op_mov:
>       case INDEX_op_neg:
>       case INDEX_op_not:
>       case INDEX_op_ext_i32_i64:
>       case INDEX_op_extu_i32_i64:
> -    case INDEX_op_bswap32_i32:
> -    case INDEX_op_bswap32_i64:
>       case INDEX_op_bswap64_i64:
>           tci_args_rr(insn, &r0, &r1);
>           info->fprintf_func(info->stream, "%-12s  %s, %s",
> diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst
> index 509cfe7db1..e89ede54fa 100644
> --- a/docs/devel/tcg-ops.rst
> +++ b/docs/devel/tcg-ops.rst
> @@ -425,16 +425,15 @@ Misc
>          |
>          | If neither ``TCG_BSWAP_OZ`` nor ``TCG_BSWAP_OS`` are set, then the bits of *t0* above bit 15 may contain any value.
>   
> -   * - bswap32_i64 *t0*, *t1*, *flags*
> +   * - bswap32 *t0*, *t1*, *flags*
>   
> -     - | 32 bit byte swap on a 64-bit value.  The flags are the same as for bswap16,
> -         except they apply from bit 31 instead of bit 15.
> +     - | 32 bit byte swap.  The flags are the same as for bswap16, except
> +         they apply from bit 31 instead of bit 15.  On TCG_TYPE_I32, the
> +         flags should be zero.
>   
> -   * - bswap32_i32 *t0*, *t1*, *flags*
> +   * - bswap64_i64 *t0*, *t1*, *flags*
>   
> -       bswap64_i64 *t0*, *t1*, *flags*
> -
> -     - | 32/64 bit byte swap. The flags are ignored, but still present
> +     - | 64 bit byte swap. The flags are ignored, but still present
>            for consistency with the other bswap opcodes.
>   
>      * - discard_i32/i64 *t0*
> diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
> index 1b2f18e370..7478ada393 100644
> --- a/tcg/tci/tcg-target.c.inc
> +++ b/tcg/tci/tcg-target.c.inc
> @@ -917,7 +917,7 @@ static const TCGOutOpBswap outop_bswap16 = {
>   static void tgen_bswap32(TCGContext *s, TCGType type,
>                            TCGReg a0, TCGReg a1, unsigned flags)
>   {
> -    tcg_out_op_rr(s, INDEX_op_bswap32_i32, a0, a1);
> +    tcg_out_op_rr(s, INDEX_op_bswap32, a0, a1);
>       if (flags & TCG_BSWAP_OS) {
>           tcg_out_sextract(s, TCG_TYPE_REG, a0, a0, 0, 32);
>       }

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff mbox series

Patch

diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index acfbaa05b4..296dffe99a 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -44,6 +44,7 @@  DEF(add, 1, 2, 0, TCG_OPF_INT)
 DEF(and, 1, 2, 0, TCG_OPF_INT)
 DEF(andc, 1, 2, 0, TCG_OPF_INT)
 DEF(bswap16, 1, 1, 1, TCG_OPF_INT)
+DEF(bswap32, 1, 1, 1, TCG_OPF_INT)
 DEF(clz, 1, 2, 0, TCG_OPF_INT)
 DEF(ctpop, 1, 1, 0, TCG_OPF_INT)
 DEF(ctz, 1, 2, 0, TCG_OPF_INT)
@@ -96,8 +97,6 @@  DEF(sub2_i32, 2, 4, 0, 0)
 DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
 DEF(setcond2_i32, 1, 4, 1, 0)
 
-DEF(bswap32_i32, 1, 1, 1, 0)
-
 /* load/store */
 DEF(ld8u_i64, 1, 1, 1, 0)
 DEF(ld8s_i64, 1, 1, 1, 0)
@@ -122,7 +121,6 @@  DEF(extu_i32_i64, 1, 1, 0, 0)
 DEF(extrl_i64_i32, 1, 1, 0, 0)
 DEF(extrh_i64_i32, 1, 1, 0, 0)
 
-DEF(bswap32_i64, 1, 1, 1, 0)
 DEF(bswap64_i64, 1, 1, 1, 0)
 
 DEF(add2_i64, 2, 4, 0, 0)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 75849a1495..be9d09467d 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -510,7 +510,7 @@  static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type,
         x = bswap16(x);
         return y & TCG_BSWAP_OS ? (int16_t)x : x;
 
-    CASE_OP_32_64(bswap32):
+    case INDEX_op_bswap32:
         x = bswap32(x);
         return y & TCG_BSWAP_OS ? (int32_t)x : x;
 
@@ -1564,8 +1564,7 @@  static bool fold_bswap(OptContext *ctx, TCGOp *op)
         z_mask = bswap16(z_mask);
         sign = INT16_MIN;
         break;
-    case INDEX_op_bswap32_i32:
-    case INDEX_op_bswap32_i64:
+    case INDEX_op_bswap32:
         z_mask = bswap32(z_mask);
         sign = INT32_MIN;
         break;
@@ -2858,7 +2857,7 @@  void tcg_optimize(TCGContext *s)
             done = fold_brcond2(&ctx, op);
             break;
         case INDEX_op_bswap16:
-        CASE_OP_32_64(bswap32):
+        case INDEX_op_bswap32:
         case INDEX_op_bswap64_i64:
             done = fold_bswap(&ctx, op);
             break;
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 68e53a9c85..b1174f60cc 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1294,8 +1294,8 @@  void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags)
  */
 void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
 {
-    if (tcg_op_supported(INDEX_op_bswap32_i32, TCG_TYPE_I32, 0)) {
-        tcg_gen_op3i_i32(INDEX_op_bswap32_i32, ret, arg, 0);
+    if (tcg_op_supported(INDEX_op_bswap32, TCG_TYPE_I32, 0)) {
+        tcg_gen_op3i_i32(INDEX_op_bswap32, ret, arg, 0);
     } else {
         TCGv_i32 t0 = tcg_temp_ebb_new_i32();
         TCGv_i32 t1 = tcg_temp_ebb_new_i32();
@@ -2137,8 +2137,8 @@  void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags)
         } else {
             tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
         }
-    } else if (tcg_op_supported(INDEX_op_bswap32_i64, TCG_TYPE_I64, 0)) {
-        tcg_gen_op3i_i64(INDEX_op_bswap32_i64, ret, arg, flags);
+    } else if (tcg_op_supported(INDEX_op_bswap32, TCG_TYPE_I64, 0)) {
+        tcg_gen_op3i_i64(INDEX_op_bswap32, ret, arg, flags);
     } else {
         TCGv_i64 t0 = tcg_temp_ebb_new_i64();
         TCGv_i64 t1 = tcg_temp_ebb_new_i64();
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 117021f610..51f9cc7fe1 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1076,8 +1076,7 @@  static const TCGOutOp * const all_outop[NB_OPS] = {
     OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
     OUTOP(INDEX_op_brcond, TCGOutOpBrcond, outop_brcond),
     OUTOP(INDEX_op_bswap16, TCGOutOpBswap, outop_bswap16),
-    OUTOP(INDEX_op_bswap32_i32, TCGOutOpBswap, outop_bswap32),
-    OUTOP(INDEX_op_bswap32_i64, TCGOutOpBswap, outop_bswap32),
+    OUTOP(INDEX_op_bswap32, TCGOutOpBswap, outop_bswap32),
     OUTOP(INDEX_op_clz, TCGOutOpBinary, outop_clz),
     OUTOP(INDEX_op_ctpop, TCGOutOpUnary, outop_ctpop),
     OUTOP(INDEX_op_ctz, TCGOutOpBinary, outop_ctz),
@@ -2939,8 +2938,7 @@  void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs)
                 }
                 break;
             case INDEX_op_bswap16:
-            case INDEX_op_bswap32_i32:
-            case INDEX_op_bswap32_i64:
+            case INDEX_op_bswap32:
             case INDEX_op_bswap64_i64:
                 {
                     TCGArg flags = op->args[k];
@@ -5483,8 +5481,7 @@  static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
         break;
 
     case INDEX_op_bswap16:
-    case INDEX_op_bswap32_i32:
-    case INDEX_op_bswap32_i64:
+    case INDEX_op_bswap32:
         {
             const TCGOutOpBswap *out =
                 container_of(all_outop[op->opc], TCGOutOpBswap, base);
diff --git a/tcg/tci.c b/tcg/tci.c
index 0cb89f3256..f98c437100 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -690,7 +690,7 @@  uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
             tci_args_rr(insn, &r0, &r1);
             regs[r0] = bswap16(regs[r1]);
             break;
-        CASE_32_64(bswap32)
+        case INDEX_op_bswap32:
             tci_args_rr(insn, &r0, &r1);
             regs[r0] = bswap32(regs[r1]);
             break;
@@ -1004,14 +1004,13 @@  int print_insn_tci(bfd_vma addr, disassemble_info *info)
         break;
 
     case INDEX_op_bswap16:
+    case INDEX_op_bswap32:
     case INDEX_op_ctpop:
     case INDEX_op_mov:
     case INDEX_op_neg:
     case INDEX_op_not:
     case INDEX_op_ext_i32_i64:
     case INDEX_op_extu_i32_i64:
-    case INDEX_op_bswap32_i32:
-    case INDEX_op_bswap32_i64:
     case INDEX_op_bswap64_i64:
         tci_args_rr(insn, &r0, &r1);
         info->fprintf_func(info->stream, "%-12s  %s, %s",
diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst
index 509cfe7db1..e89ede54fa 100644
--- a/docs/devel/tcg-ops.rst
+++ b/docs/devel/tcg-ops.rst
@@ -425,16 +425,15 @@  Misc
        |
        | If neither ``TCG_BSWAP_OZ`` nor ``TCG_BSWAP_OS`` are set, then the bits of *t0* above bit 15 may contain any value.
 
-   * - bswap32_i64 *t0*, *t1*, *flags*
+   * - bswap32 *t0*, *t1*, *flags*
 
-     - | 32 bit byte swap on a 64-bit value.  The flags are the same as for bswap16,
-         except they apply from bit 31 instead of bit 15.
+     - | 32 bit byte swap.  The flags are the same as for bswap16, except
+         they apply from bit 31 instead of bit 15.  On TCG_TYPE_I32, the
+         flags should be zero.
 
-   * - bswap32_i32 *t0*, *t1*, *flags*
+   * - bswap64_i64 *t0*, *t1*, *flags*
 
-       bswap64_i64 *t0*, *t1*, *flags*
-
-     - | 32/64 bit byte swap. The flags are ignored, but still present
+     - | 64 bit byte swap. The flags are ignored, but still present
          for consistency with the other bswap opcodes.
 
    * - discard_i32/i64 *t0*
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 1b2f18e370..7478ada393 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -917,7 +917,7 @@  static const TCGOutOpBswap outop_bswap16 = {
 static void tgen_bswap32(TCGContext *s, TCGType type,
                          TCGReg a0, TCGReg a1, unsigned flags)
 {
-    tcg_out_op_rr(s, INDEX_op_bswap32_i32, a0, a1);
+    tcg_out_op_rr(s, INDEX_op_bswap32, a0, a1);
     if (flags & TCG_BSWAP_OS) {
         tcg_out_sextract(s, TCG_TYPE_REG, a0, a0, 0, 32);
     }