| Message ID | 20250415192515.232910-122-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: Convert to TCGOutOp structures | expand |
On 4/15/25 12:24, Richard Henderson wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/i386/tcg-target-con-set.h | 1 - > tcg/i386/tcg-target-has.h | 8 ++++---- > tcg/i386/tcg-target.c.inc | 31 ------------------------------- > 3 files changed, 4 insertions(+), 36 deletions(-) > > diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h > index 0ae9775944..85c93836bb 100644 > --- a/tcg/i386/tcg-target-con-set.h > +++ b/tcg/i386/tcg-target-con-set.h > @@ -57,4 +57,3 @@ C_O2_I1(r, r, L) > C_O2_I2(a, d, a, r) > C_O2_I2(r, r, L, L) > C_O2_I3(a, d, 0, 1, r) > -C_N1_O1_I4(r, r, 0, 1, re, re) > diff --git a/tcg/i386/tcg-target-has.h b/tcg/i386/tcg-target-has.h > index 0328102c2a..a984a6af2e 100644 > --- a/tcg/i386/tcg-target-has.h > +++ b/tcg/i386/tcg-target-has.h > @@ -26,14 +26,14 @@ > #define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl) > > /* optional instructions */ > -#define TCG_TARGET_HAS_add2_i32 1 > -#define TCG_TARGET_HAS_sub2_i32 1 > +#define TCG_TARGET_HAS_add2_i32 0 > +#define TCG_TARGET_HAS_sub2_i32 0 > > #if TCG_TARGET_REG_BITS == 64 > /* Keep 32-bit values zero-extended in a register. */ > #define TCG_TARGET_HAS_extr_i64_i32 1 > -#define TCG_TARGET_HAS_add2_i64 1 > -#define TCG_TARGET_HAS_sub2_i64 1 > +#define TCG_TARGET_HAS_add2_i64 0 > +#define TCG_TARGET_HAS_sub2_i64 0 > #define TCG_TARGET_HAS_qemu_st8_i32 0 > #else > #define TCG_TARGET_HAS_qemu_st8_i32 1 > diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc > index 52d3402f29..44f9afc0d6 100644 > --- a/tcg/i386/tcg-target.c.inc > +++ b/tcg/i386/tcg-target.c.inc > @@ -3479,31 +3479,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I128); > break; > > - OP_32_64(add2): > - if (const_args[4]) { > - tgen_arithi(s, ARITH_ADD + rexw, a0, args[4], 1); > - } else { > - tgen_arithr(s, ARITH_ADD + rexw, a0, args[4]); > - } > - if (const_args[5]) { > - tgen_arithi(s, ARITH_ADC + rexw, a1, args[5], 1); > - } else { > - tgen_arithr(s, ARITH_ADC + rexw, a1, args[5]); > - } > - break; > - OP_32_64(sub2): > - if (const_args[4]) { > - tgen_arithi(s, ARITH_SUB + rexw, a0, args[4], 1); > - } else { > - tgen_arithr(s, ARITH_SUB + rexw, a0, args[4]); > - } > - if (const_args[5]) { > - tgen_arithi(s, ARITH_SBB + rexw, a1, args[5], 1); > - } else { > - tgen_arithr(s, ARITH_SBB + rexw, a1, args[5]); > - } > - break; > - > #if TCG_TARGET_REG_BITS == 64 > case INDEX_op_ld32s_i64: > tcg_out_modrm_offset(s, OPC_MOVSLQ, a0, a1, a2); > @@ -4109,12 +4084,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > case INDEX_op_st_i64: > return C_O0_I2(re, r); > > - case INDEX_op_add2_i32: > - case INDEX_op_add2_i64: > - case INDEX_op_sub2_i32: > - case INDEX_op_sub2_i64: > - return C_N1_O1_I4(r, r, 0, 1, re, re); > - > case INDEX_op_qemu_ld_i32: > return C_O1_I1(r, L); > Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h index 0ae9775944..85c93836bb 100644 --- a/tcg/i386/tcg-target-con-set.h +++ b/tcg/i386/tcg-target-con-set.h @@ -57,4 +57,3 @@ C_O2_I1(r, r, L) C_O2_I2(a, d, a, r) C_O2_I2(r, r, L, L) C_O2_I3(a, d, 0, 1, r) -C_N1_O1_I4(r, r, 0, 1, re, re) diff --git a/tcg/i386/tcg-target-has.h b/tcg/i386/tcg-target-has.h index 0328102c2a..a984a6af2e 100644 --- a/tcg/i386/tcg-target-has.h +++ b/tcg/i386/tcg-target-has.h @@ -26,14 +26,14 @@ #define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl) /* optional instructions */ -#define TCG_TARGET_HAS_add2_i32 1 -#define TCG_TARGET_HAS_sub2_i32 1 +#define TCG_TARGET_HAS_add2_i32 0 +#define TCG_TARGET_HAS_sub2_i32 0 #if TCG_TARGET_REG_BITS == 64 /* Keep 32-bit values zero-extended in a register. */ #define TCG_TARGET_HAS_extr_i64_i32 1 -#define TCG_TARGET_HAS_add2_i64 1 -#define TCG_TARGET_HAS_sub2_i64 1 +#define TCG_TARGET_HAS_add2_i64 0 +#define TCG_TARGET_HAS_sub2_i64 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 #else #define TCG_TARGET_HAS_qemu_st8_i32 1 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 52d3402f29..44f9afc0d6 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -3479,31 +3479,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I128); break; - OP_32_64(add2): - if (const_args[4]) { - tgen_arithi(s, ARITH_ADD + rexw, a0, args[4], 1); - } else { - tgen_arithr(s, ARITH_ADD + rexw, a0, args[4]); - } - if (const_args[5]) { - tgen_arithi(s, ARITH_ADC + rexw, a1, args[5], 1); - } else { - tgen_arithr(s, ARITH_ADC + rexw, a1, args[5]); - } - break; - OP_32_64(sub2): - if (const_args[4]) { - tgen_arithi(s, ARITH_SUB + rexw, a0, args[4], 1); - } else { - tgen_arithr(s, ARITH_SUB + rexw, a0, args[4]); - } - if (const_args[5]) { - tgen_arithi(s, ARITH_SBB + rexw, a1, args[5], 1); - } else { - tgen_arithr(s, ARITH_SBB + rexw, a1, args[5]); - } - break; - #if TCG_TARGET_REG_BITS == 64 case INDEX_op_ld32s_i64: tcg_out_modrm_offset(s, OPC_MOVSLQ, a0, a1, a2); @@ -4109,12 +4084,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) case INDEX_op_st_i64: return C_O0_I2(re, r); - case INDEX_op_add2_i32: - case INDEX_op_add2_i64: - case INDEX_op_sub2_i32: - case INDEX_op_sub2_i64: - return C_N1_O1_I4(r, r, 0, 1, re, re); - case INDEX_op_qemu_ld_i32: return C_O1_I1(r, L);
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/i386/tcg-target-con-set.h | 1 - tcg/i386/tcg-target-has.h | 8 ++++---- tcg/i386/tcg-target.c.inc | 31 ------------------------------- 3 files changed, 4 insertions(+), 36 deletions(-)