| Message ID | 20250404115539.1151201-8-quic_amakhija@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add DSI display support for SA8775P target | expand |
On Fri, Apr 04, 2025 at 05:25:36PM +0530, Ayushi Makhija wrote: > Add anx7625 DSI to DP bridge device nodes. > > Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 208 ++++++++++++++++++++- > 1 file changed, 207 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi > index 175f8b1e3b2d..8e784ccf4138 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi > @@ -28,6 +28,13 @@ chosen { > stdout-path = "serial0:115200n8"; > }; > > + vph_pwr: vph-pwr-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "vph_pwr"; > + regulator-always-on; > + regulator-boot-on; > + }; > + > vreg_conn_1p8: vreg_conn_1p8 { > compatible = "regulator-fixed"; > regulator-name = "vreg_conn_1p8"; > @@ -128,6 +135,30 @@ dp1_connector_in: endpoint { > }; > }; > }; > + > + dp-dsi0-connector { > + compatible = "dp-connector"; > + label = "DSI0"; > + type = "full-size"; > + > + port { > + dp_dsi0_connector_in: endpoint { > + remote-endpoint = <&dsi2dp_bridge0_out>; > + }; > + }; > + }; > + > + dp-dsi1-connector { > + compatible = "dp-connector"; > + label = "DSI1"; > + type = "full-size"; > + > + port { > + dp_dsi1_connector_in: endpoint { > + remote-endpoint = <&dsi2dp_bridge1_out>; > + }; > + }; > + }; > }; > > &apps_rsc { > @@ -517,9 +548,135 @@ &i2c11 { > > &i2c18 { > clock-frequency = <400000>; > - pinctrl-0 = <&qup_i2c18_default>; > + pinctrl-0 = <&qup_i2c18_default>, > + <&io_expander_intr_active>, > + <&io_expander_reset_active>; These pinctrl entries should go to the IO expander itself. > pinctrl-names = "default"; > + > status = "okay"; > + > + io_expander: gpio@74 { > + compatible = "ti,tca9539"; > + reg = <0x74>; > + interrupts-extended = <&tlmm 98 IRQ_TYPE_EDGE_BOTH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + > + gpio2-hog { This needs a huuge explanation in the commit message. Otherwise I'd say these pins should likely be used by the corresponding anx bridges. > + gpio-hog; > + gpios = <2 GPIO_ACTIVE_HIGH>; > + input; > + line-name = "dsi0_int_pin"; > + }; > + > + gpio3-hog { > + gpio-hog; > + gpios = <3 GPIO_ACTIVE_LOW>; > + output-high; > + line-name = "dsi0_cbl_det_pin"; > + }; > + > + gpio10-hog { > + gpio-hog; > + gpios = <10 GPIO_ACTIVE_HIGH>; > + input; > + line-name = "dsi1_int_pin"; > + }; > + > + gpio11-hog { > + gpio-hog; > + gpios = <11 GPIO_ACTIVE_LOW>; > + output-high; > + line-name = "dsi1_cbl_det_pin"; > + }; > + }; > + > + i2c-mux@70 { > + compatible = "nxp,pca9543"; > + #address-cells = <1>; > + > + #size-cells = <0>; > + reg = <0x70>; > + > + i2c@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + bridge@58 { > + compatible = "analogix,anx7625"; > + reg = <0x58>; > + interrupts-extended = <&io_expander 2 IRQ_TYPE_EDGE_FALLING>; > + enable-gpios = <&io_expander 1 GPIO_ACTIVE_HIGH>; > + reset-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>; > + vdd10-supply = <&vph_pwr>; > + vdd18-supply = <&vph_pwr>; > + vdd33-supply = <&vph_pwr>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + dsi2dp_bridge0_in: endpoint { > + remote-endpoint = <&mdss0_dsi0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + dsi2dp_bridge0_out: endpoint { > + remote-endpoint = <&dp_dsi0_connector_in>; > + }; > + }; > + }; > + }; > + }; > + > + i2c@1 { > + reg = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + bridge@58 { > + compatible = "analogix,anx7625"; > + reg = <0x58>; > + interrupts-extended = <&io_expander 10 IRQ_TYPE_EDGE_FALLING>; > + enable-gpios = <&io_expander 9 GPIO_ACTIVE_HIGH>; > + reset-gpios = <&io_expander 8 GPIO_ACTIVE_HIGH>; > + vdd10-supply = <&vph_pwr>; > + vdd18-supply = <&vph_pwr>; > + vdd33-supply = <&vph_pwr>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + dsi2dp_bridge1_in: endpoint { > + remote-endpoint = <&mdss0_dsi1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + dsi2dp_bridge1_out: endpoint { > + remote-endpoint = <&dp_dsi1_connector_in>; > + }; > + }; > + }; > + }; > + }; > + }; > + > }; > > &mdss0 { > @@ -566,6 +723,40 @@ &mdss0_dp1_phy { > status = "okay"; > }; > > +&mdss0_dsi0 { > + vdda-supply = <&vreg_l1c>; > + > + status = "okay"; > +}; > + > +&mdss0_dsi0_out { > + data-lanes = <0 1 2 3>; > + remote-endpoint = <&dsi2dp_bridge0_in>; > +}; > + > +&mdss0_dsi0_phy { > + vdds-supply = <&vreg_l4a>; > + > + status = "okay"; > +}; > + > +&mdss0_dsi1 { > + vdda-supply = <&vreg_l1c>; > + > + status = "okay"; > +}; > + > +&mdss0_dsi1_out { > + data-lanes = <0 1 2 3>; > + remote-endpoint = <&dsi2dp_bridge1_in>; > +}; > + > +&mdss0_dsi1_phy { > + vdds-supply = <&vreg_l4a>; > + > + status = "okay"; > +}; > + > &pmm8654au_0_gpios { > gpio-line-names = "DS_EN", > "POFF_COMPLETE", > @@ -714,6 +905,21 @@ ethernet0_mdio: ethernet0-mdio-pins { > }; > }; > > + io_expander_intr_active: io-expander-intr-active-state { > + pins = "gpio98"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + io_expander_reset_active: io-expander-reset-active-state { > + pins = "gpio97"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + output-high; > + }; > + > qup_uart10_default: qup-uart10-state { > pins = "gpio46", "gpio47"; > function = "qup1_se3"; > -- > 2.34.1 >
On 4/7/2025 1:42 AM, Dmitry Baryshkov wrote: > On Fri, Apr 04, 2025 at 05:25:36PM +0530, Ayushi Makhija wrote: >> Add anx7625 DSI to DP bridge device nodes. >> >> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 208 ++++++++++++++++++++- >> 1 file changed, 207 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi >> index 175f8b1e3b2d..8e784ccf4138 100644 >> --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi >> @@ -28,6 +28,13 @@ chosen { >> stdout-path = "serial0:115200n8"; >> }; >> >> + vph_pwr: vph-pwr-regulator { >> + compatible = "regulator-fixed"; >> + regulator-name = "vph_pwr"; >> + regulator-always-on; >> + regulator-boot-on; >> + }; >> + >> vreg_conn_1p8: vreg_conn_1p8 { >> compatible = "regulator-fixed"; >> regulator-name = "vreg_conn_1p8"; >> @@ -128,6 +135,30 @@ dp1_connector_in: endpoint { >> }; >> }; >> }; >> + >> + dp-dsi0-connector { >> + compatible = "dp-connector"; >> + label = "DSI0"; >> + type = "full-size"; >> + >> + port { >> + dp_dsi0_connector_in: endpoint { >> + remote-endpoint = <&dsi2dp_bridge0_out>; >> + }; >> + }; >> + }; >> + >> + dp-dsi1-connector { >> + compatible = "dp-connector"; >> + label = "DSI1"; >> + type = "full-size"; >> + >> + port { >> + dp_dsi1_connector_in: endpoint { >> + remote-endpoint = <&dsi2dp_bridge1_out>; >> + }; >> + }; >> + }; >> }; >> >> &apps_rsc { >> @@ -517,9 +548,135 @@ &i2c11 { >> >> &i2c18 { >> clock-frequency = <400000>; >> - pinctrl-0 = <&qup_i2c18_default>; >> + pinctrl-0 = <&qup_i2c18_default>, >> + <&io_expander_intr_active>, >> + <&io_expander_reset_active>; > > These pinctrl entries should go to the IO expander itself. Will move these pinctrl entries in IO expander in next patchset. Thanks, Ayushi
On Thu, Apr 10, 2025 at 06:37:54PM +0530, Ayushi Makhija wrote: > Hi Dmirity/Konard > > On 4/7/2025 1:42 AM, Dmitry Baryshkov wrote: > > On Fri, Apr 04, 2025 at 05:25:36PM +0530, Ayushi Makhija wrote: > >> Add anx7625 DSI to DP bridge device nodes. > >> > >> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com> > >> --- > >> arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 208 ++++++++++++++++++++- > >> 1 file changed, 207 insertions(+), 1 deletion(-) > >> > >> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi > >> index 175f8b1e3b2d..8e784ccf4138 100644 > >> --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi > >> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi > >> @@ -28,6 +28,13 @@ chosen { > >> stdout-path = "serial0:115200n8"; > >> }; > >> > >> + vph_pwr: vph-pwr-regulator { > >> + compatible = "regulator-fixed"; > >> + regulator-name = "vph_pwr"; > >> + regulator-always-on; > >> + regulator-boot-on; > >> + }; > >> + > >> vreg_conn_1p8: vreg_conn_1p8 { > >> compatible = "regulator-fixed"; > >> regulator-name = "vreg_conn_1p8"; > >> @@ -128,6 +135,30 @@ dp1_connector_in: endpoint { > >> }; > >> }; > >> }; > >> + > >> + dp-dsi0-connector { > >> + compatible = "dp-connector"; > >> + label = "DSI0"; > >> + type = "full-size"; > >> + > >> + port { > >> + dp_dsi0_connector_in: endpoint { > >> + remote-endpoint = <&dsi2dp_bridge0_out>; > >> + }; > >> + }; > >> + }; > >> + > >> + dp-dsi1-connector { > >> + compatible = "dp-connector"; > >> + label = "DSI1"; > >> + type = "full-size"; > >> + > >> + port { > >> + dp_dsi1_connector_in: endpoint { > >> + remote-endpoint = <&dsi2dp_bridge1_out>; > >> + }; > >> + }; > >> + }; > >> }; > >> > >> &apps_rsc { > >> @@ -517,9 +548,135 @@ &i2c11 { > >> > >> &i2c18 { > >> clock-frequency = <400000>; > >> - pinctrl-0 = <&qup_i2c18_default>; > >> + pinctrl-0 = <&qup_i2c18_default>, > >> + <&io_expander_intr_active>, > >> + <&io_expander_reset_active>; > > > > These pinctrl entries should go to the IO expander itself. > > > >> pinctrl-names = "default"; > >> + > >> status = "okay"; > >> + > >> + io_expander: gpio@74 { > >> + compatible = "ti,tca9539"; > >> + reg = <0x74>; > >> + interrupts-extended = <&tlmm 98 IRQ_TYPE_EDGE_BOTH>; > >> + gpio-controller; > >> + #gpio-cells = <2>; > >> + interrupt-controller; > >> + #interrupt-cells = <2>; > >> + > >> + gpio2-hog { > > > > This needs a huuge explanation in the commit message. Otherwise I'd say > > these pins should likely be used by the corresponding anx bridges. > > Thanks, for the review. > > Previously, I was referring to the downstream DT and misunderstood the use of gpio-hog. > After reading the schematic, I realized that gpio2, gpio3, gpio10, and gpio11 are all input pins > to the IO expander TC9539. We have already configured gpio2 and gpio10 as interrupts in the > ANX7625 bridges, so the gpio-hog is not required. It is working without the gpio-hog configuration. Please make sure that there are pinctrl entries for all pins.
On 4/14/2025 3:37 PM, Dmitry Baryshkov wrote: > On 14/04/2025 12:56, Ayushi Makhija wrote: >> Hi Dmitry, >> >> On 4/11/2025 1:31 AM, Dmitry Baryshkov wrote: >>> On Thu, Apr 10, 2025 at 06:37:54PM +0530, Ayushi Makhija wrote: >>>> Hi Dmirity/Konard >>>> >>>> On 4/7/2025 1:42 AM, Dmitry Baryshkov wrote: >>>>> On Fri, Apr 04, 2025 at 05:25:36PM +0530, Ayushi Makhija wrote: >>>>>> Add anx7625 DSI to DP bridge device nodes. >>>>>> >>>>>> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com> >>>>>> --- >>>>>> arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 208 ++++++++++++++++++++- >>>>>> 1 file changed, 207 insertions(+), 1 deletion(-) >>>>>> >>>>>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi >>>>>> index 175f8b1e3b2d..8e784ccf4138 100644 >>>>>> --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi >>>>>> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi >>>>>> @@ -28,6 +28,13 @@ chosen { >>>>>> stdout-path = "serial0:115200n8"; >>>>>> }; >>>>>> + vph_pwr: vph-pwr-regulator { >>>>>> + compatible = "regulator-fixed"; >>>>>> + regulator-name = "vph_pwr"; >>>>>> + regulator-always-on; >>>>>> + regulator-boot-on; >>>>>> + }; >>>>>> + >>>>>> vreg_conn_1p8: vreg_conn_1p8 { >>>>>> compatible = "regulator-fixed"; >>>>>> regulator-name = "vreg_conn_1p8"; >>>>>> @@ -128,6 +135,30 @@ dp1_connector_in: endpoint { >>>>>> }; >>>>>> }; >>>>>> }; >>>>>> + >>>>>> + dp-dsi0-connector { >>>>>> + compatible = "dp-connector"; >>>>>> + label = "DSI0"; >>>>>> + type = "full-size"; >>>>>> + >>>>>> + port { >>>>>> + dp_dsi0_connector_in: endpoint { >>>>>> + remote-endpoint = <&dsi2dp_bridge0_out>; >>>>>> + }; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + dp-dsi1-connector { >>>>>> + compatible = "dp-connector"; >>>>>> + label = "DSI1"; >>>>>> + type = "full-size"; >>>>>> + >>>>>> + port { >>>>>> + dp_dsi1_connector_in: endpoint { >>>>>> + remote-endpoint = <&dsi2dp_bridge1_out>; >>>>>> + }; >>>>>> + }; >>>>>> + }; >>>>>> }; >>>>>> &apps_rsc { >>>>>> @@ -517,9 +548,135 @@ &i2c11 { >>>>>> &i2c18 { >>>>>> clock-frequency = <400000>; >>>>>> - pinctrl-0 = <&qup_i2c18_default>; >>>>>> + pinctrl-0 = <&qup_i2c18_default>, >>>>>> + <&io_expander_intr_active>, >>>>>> + <&io_expander_reset_active>; >>>>> >>>>> These pinctrl entries should go to the IO expander itself. >>>>> >>>>>> pinctrl-names = "default"; >>>>>> + >>>>>> status = "okay"; >>>>>> + >>>>>> + io_expander: gpio@74 { >>>>>> + compatible = "ti,tca9539"; >>>>>> + reg = <0x74>; >>>>>> + interrupts-extended = <&tlmm 98 IRQ_TYPE_EDGE_BOTH>; >>>>>> + gpio-controller; >>>>>> + #gpio-cells = <2>; >>>>>> + interrupt-controller; >>>>>> + #interrupt-cells = <2>; >>>>>> + >>>>>> + gpio2-hog { >>>>> >>>>> This needs a huuge explanation in the commit message. Otherwise I'd say >>>>> these pins should likely be used by the corresponding anx bridges. >>>> >>>> Thanks, for the review. >>>> >>>> Previously, I was referring to the downstream DT and misunderstood the use of gpio-hog. >>>> After reading the schematic, I realized that gpio2, gpio3, gpio10, and gpio11 are all input pins >>>> to the IO expander TC9539. We have already configured gpio2 and gpio10 as interrupts in the >>>> ANX7625 bridges, so the gpio-hog is not required. It is working without the gpio-hog configuration. >>> >>> Please make sure that there are pinctrl entries for all pins. >>> >> >> Thanks, for the review. >> >> While declaring the pinctrl entries inside the io_expander node, I am getting below error while checking the DTBS check against DT-binding. >> >> Error : /local/mnt/workspace/amakhija/linux_next_11042025/linux/arch/arm64/boot/dts/qcom/sa8775p-ride.dtb: gpio@74: 'dsi0-int-pin-state', 'dsi1-int-pin-state' do not match any of the regexes: >> '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$', 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/gpio/gpio-pca95xx.yaml# > > TCA9539 is a GPIO controller rather than a pinctrl device, so it doesn't use pinctrl functions. You don't need to describe properties of the pins that it provides. However, it can use some pins on its own (like reset-gpios). In such a case corresponding pin should have a pinctrl configuration under its pinctrl device. > Hi Dmitry, Thanks, for the review. ______________ _____________________ ___________________ | | | | | | | GPIO 98|---ioexp_intr-->| GPIO 0 |------Reset--------->|RESET_N | | GPIO 97|<--ioexp_reset--| GPIO 1 |----power-enable---->|POWER_EN | | | | | | | | SOC | | tca9539 | | anx7625 bridge | | LeMans | | io_expander | | | | | | GPIO 2 |<----DSI0_INT_1P8_N--|ALERT_N/INTP | |______________| |_____________________| |___________________| Based on the above connection diagram, I have already configured the reset(gpio0), power-enable(gpio1) and interrupt (ALERT_N/INTP) (gpio2) for first instance of anx7625 bridge. Similarly I have configured the reset(gpio8), power-enable(gpio9) and interrupt (gpio10) for the second instance of the anx7625 bridge. bridge@58 { compatible = "analogix,anx7625"; reg = <0x58>; interrupts-extended = <&io_expander 2 IRQ_TYPE_EDGE_FALLING>; enable-gpios = <&io_expander 1 GPIO_ACTIVE_HIGH>; reset-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>; I think above configuration should be fine, we don't need any pinctrl for io expander's gpios going to anx7625 bridge. Other two RESET (gpio97) and INTR (gpio98) gpios, which is connecting SOC to io expander (tca9539), I have already declared them under tlmm node. io_expander_intr_active: io-expander-intr-active-state { pins = "gpio98"; function = "gpio"; drive-strength = <2>; bias-disable; }; io_expander_reset_active: io-expander-reset-active-state { pins = "gpio97"; function = "gpio"; drive-strength = <2>; bias-disable; output-high; }; Thanks, Ayushi >> >> io_expander: gpio@74 { >> compatible = "ti,tca9539"; >> reg = <0x74>; >> interrupts-extended = <&tlmm 98 IRQ_TYPE_EDGE_BOTH>; >> gpio-controller; >> #gpio-cells = <2>; >> interrupt-controller; >> #interrupt-cells = <2>; >> >> pinctrl-0 = <&io_expander_intr_active>, >> <&io_expander_reset_active>; >> pinctrl-names = "default"; >> >> dsi0_int_pin: dsi0-int-pin-state { >> pins = "gpio2"; >> input-enable; >> bias-disable; >> }; >> >> dsi1_int_pin: dsi1-int-pin-state { >> pins = "gpio10"; >> input-enable; >> bias-disable; >> }; >> >> }; >> >> I couldn't find any devicetree example of tca9539 which is using pinctrl. The gpio-pca95xx.yaml DT binding does not match with any regex of the patterns properties. >> >> Thanks, >> Ayushi > >
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi index 175f8b1e3b2d..8e784ccf4138 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -28,6 +28,13 @@ chosen { stdout-path = "serial0:115200n8"; }; + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; + vreg_conn_1p8: vreg_conn_1p8 { compatible = "regulator-fixed"; regulator-name = "vreg_conn_1p8"; @@ -128,6 +135,30 @@ dp1_connector_in: endpoint { }; }; }; + + dp-dsi0-connector { + compatible = "dp-connector"; + label = "DSI0"; + type = "full-size"; + + port { + dp_dsi0_connector_in: endpoint { + remote-endpoint = <&dsi2dp_bridge0_out>; + }; + }; + }; + + dp-dsi1-connector { + compatible = "dp-connector"; + label = "DSI1"; + type = "full-size"; + + port { + dp_dsi1_connector_in: endpoint { + remote-endpoint = <&dsi2dp_bridge1_out>; + }; + }; + }; }; &apps_rsc { @@ -517,9 +548,135 @@ &i2c11 { &i2c18 { clock-frequency = <400000>; - pinctrl-0 = <&qup_i2c18_default>; + pinctrl-0 = <&qup_i2c18_default>, + <&io_expander_intr_active>, + <&io_expander_reset_active>; pinctrl-names = "default"; + status = "okay"; + + io_expander: gpio@74 { + compatible = "ti,tca9539"; + reg = <0x74>; + interrupts-extended = <&tlmm 98 IRQ_TYPE_EDGE_BOTH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + gpio2-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + input; + line-name = "dsi0_int_pin"; + }; + + gpio3-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-high; + line-name = "dsi0_cbl_det_pin"; + }; + + gpio10-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + input; + line-name = "dsi1_int_pin"; + }; + + gpio11-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_LOW>; + output-high; + line-name = "dsi1_cbl_det_pin"; + }; + }; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + bridge@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + interrupts-extended = <&io_expander 2 IRQ_TYPE_EDGE_FALLING>; + enable-gpios = <&io_expander 1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>; + vdd10-supply = <&vph_pwr>; + vdd18-supply = <&vph_pwr>; + vdd33-supply = <&vph_pwr>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi2dp_bridge0_in: endpoint { + remote-endpoint = <&mdss0_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + dsi2dp_bridge0_out: endpoint { + remote-endpoint = <&dp_dsi0_connector_in>; + }; + }; + }; + }; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + bridge@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + interrupts-extended = <&io_expander 10 IRQ_TYPE_EDGE_FALLING>; + enable-gpios = <&io_expander 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&io_expander 8 GPIO_ACTIVE_HIGH>; + vdd10-supply = <&vph_pwr>; + vdd18-supply = <&vph_pwr>; + vdd33-supply = <&vph_pwr>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi2dp_bridge1_in: endpoint { + remote-endpoint = <&mdss0_dsi1_out>; + }; + }; + + port@1 { + reg = <1>; + + dsi2dp_bridge1_out: endpoint { + remote-endpoint = <&dp_dsi1_connector_in>; + }; + }; + }; + }; + }; + }; + }; &mdss0 { @@ -566,6 +723,40 @@ &mdss0_dp1_phy { status = "okay"; }; +&mdss0_dsi0 { + vdda-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&mdss0_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&dsi2dp_bridge0_in>; +}; + +&mdss0_dsi0_phy { + vdds-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&mdss0_dsi1 { + vdda-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&mdss0_dsi1_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&dsi2dp_bridge1_in>; +}; + +&mdss0_dsi1_phy { + vdds-supply = <&vreg_l4a>; + + status = "okay"; +}; + &pmm8654au_0_gpios { gpio-line-names = "DS_EN", "POFF_COMPLETE", @@ -714,6 +905,21 @@ ethernet0_mdio: ethernet0-mdio-pins { }; }; + io_expander_intr_active: io-expander-intr-active-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + io_expander_reset_active: io-expander-reset-active-state { + pins = "gpio97"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + qup_uart10_default: qup-uart10-state { pins = "gpio46", "gpio47"; function = "qup1_se3";
Add anx7625 DSI to DP bridge device nodes. Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com> --- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 208 ++++++++++++++++++++- 1 file changed, 207 insertions(+), 1 deletion(-)