diff mbox series

[RFC,PATCH-for-10.1,06/19] target/tricore: Replace TARGET_LONG_BITS -> target_long_bits()

Message ID 20250403234914.9154-7-philmd@linaro.org
State New
Headers show
Series qemu: Introduce TargetInfo API (for single binary) | expand

Commit Message

Philippe Mathieu-Daudé April 3, 2025, 11:49 p.m. UTC 
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/tricore/translate.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Pierrick Bouvier April 4, 2025, 4:48 p.m. UTC | #1 
On 4/3/25 16:49, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/tricore/translate.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
> 

The temptation is good, but please do not touch any target code at this 
point. We want to focus on defining the API first, and we can perform 
codebase changes as a second step, without letting any occurrences of 
the old macros/functions, instead of just adding "another way to do it".
Philippe Mathieu-Daudé April 4, 2025, 5:53 p.m. UTC | #2 
On 4/4/25 18:48, Pierrick Bouvier wrote:
> On 4/3/25 16:49, Philippe Mathieu-Daudé wrote:
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   target/tricore/translate.c | 6 ++++--
>>   1 file changed, 4 insertions(+), 2 deletions(-)
>>
> 
> The temptation is good, but please do not touch any target code at this 
> point. We want to focus on defining the API first, and we can perform 
> codebase changes as a second step, without letting any occurrences of 
> the old macros/functions, instead of just adding "another way to do it".

I meant to remove these patch before posting, to focus on ARM, but
apparently forgot to do so...
diff mbox series

Patch

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 7cd26d8eaba..ad959f3b0a1 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -24,6 +24,7 @@ 
 #include "tcg/tcg-op.h"
 #include "accel/tcg/cpu-ldst.h"
 #include "qemu/qemu-print.h"
+#include "qemu/target_info.h"
 
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
@@ -5922,6 +5923,7 @@  static void decode_rr_logical_shift(DisasContext *ctx)
 {
     uint32_t op2;
     int r3, r2, r1;
+    unsigned long_bits = target_long_bits();
 
     r3 = MASK_OP_RR_D(ctx->opcode);
     r2 = MASK_OP_RR_S2(ctx->opcode);
@@ -5937,7 +5939,7 @@  static void decode_rr_logical_shift(DisasContext *ctx)
         break;
     case OPC2_32_RR_CLO:
         tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
-        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS);
+        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], long_bits);
         break;
     case OPC2_32_RR_CLO_H:
         gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
@@ -5949,7 +5951,7 @@  static void decode_rr_logical_shift(DisasContext *ctx)
         gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
         break;
     case OPC2_32_RR_CLZ:
-        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS);
+        tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], long_bits);
         break;
     case OPC2_32_RR_CLZ_H:
         gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);