diff mbox series

[RFC,PATCH-for-10.1,08/19] target/riscv: Replace TARGET_LONG_BITS -> target_long_bits()

Message ID 20250403234914.9154-9-philmd@linaro.org
State New
Headers show
Series qemu: Introduce TargetInfo API (for single binary) | expand

Commit Message

Philippe Mathieu-Daudé April 3, 2025, 11:49 p.m. UTC 
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/riscv/riscv-iommu.c | 3 ++-
 hw/riscv/riscv_hart.c  | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

Comments

Pierrick Bouvier April 4, 2025, 4:48 p.m. UTC | #1 
On 4/3/25 16:49, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/riscv/riscv-iommu.c | 3 ++-
>   hw/riscv/riscv_hart.c  | 3 ++-
>   2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index 65411b3e4c0..37563b2102f 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -26,6 +26,7 @@
>   #include "migration/vmstate.h"
>   #include "qapi/error.h"
>   #include "qemu/timer.h"
> +#include "qemu/target_info.h"
>   
>   #include "cpu_bits.h"
>   #include "riscv-iommu.h"
> @@ -393,7 +394,7 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
>               if (pass == S_STAGE && va_len > 32) {
>                   target_ulong mask, masked_msbs;
>   
> -                mask = (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1;
> +                mask = (1L << (target_long_bits() - (va_len - 1))) - 1;
>                   masked_msbs = (addr >> (va_len - 1)) & mask;
>   
>                   if (masked_msbs != 0 && masked_msbs != mask) {
> diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
> index a55d1566687..667d3b0a507 100644
> --- a/hw/riscv/riscv_hart.c
> +++ b/hw/riscv/riscv_hart.c
> @@ -21,6 +21,7 @@
>   #include "qemu/osdep.h"
>   #include "qapi/error.h"
>   #include "qemu/module.h"
> +#include "qemu/target_info.h"
>   #include "system/reset.h"
>   #include "system/qtest.h"
>   #include "qemu/cutils.h"
> @@ -72,7 +73,7 @@ static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val)
>           ret = riscv_csrr(env, csrno, (target_ulong *)val);
>       } else if (strcmp(cmd, "set_csr") == 0) {
>           ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val,
> -                MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
> +                MAKE_64BIT_MASK(0, target_long_bits()));
>       }
>   
>       g_assert(ret == RISCV_EXCP_NONE);

The temptation is good, but please do not touch any target code at this 
point. We want to focus on defining the API first, and we can perform 
codebase changes as a second step, without letting any occurrences of 
the old macros/functions, instead of just adding "another way to do it".
Philippe Mathieu-Daudé April 4, 2025, 5:54 p.m. UTC | #2 
On 4/4/25 18:48, Pierrick Bouvier wrote:
> On 4/3/25 16:49, Philippe Mathieu-Daudé wrote:
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   hw/riscv/riscv-iommu.c | 3 ++-
>>   hw/riscv/riscv_hart.c  | 3 ++-
>>   2 files changed, 4 insertions(+), 2 deletions(-)


> The temptation is good, but please do not touch any target code at this 
> point. We want to focus on defining the API first, and we can perform 
> codebase changes as a second step, without letting any occurrences of 
> the old macros/functions, instead of just adding "another way to do it".

I meant to remove these patch before posting, to focus on ARM, but
apparently forgot to do so...
diff mbox series

Patch

diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 65411b3e4c0..37563b2102f 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -26,6 +26,7 @@ 
 #include "migration/vmstate.h"
 #include "qapi/error.h"
 #include "qemu/timer.h"
+#include "qemu/target_info.h"
 
 #include "cpu_bits.h"
 #include "riscv-iommu.h"
@@ -393,7 +394,7 @@  static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
             if (pass == S_STAGE && va_len > 32) {
                 target_ulong mask, masked_msbs;
 
-                mask = (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1;
+                mask = (1L << (target_long_bits() - (va_len - 1))) - 1;
                 masked_msbs = (addr >> (va_len - 1)) & mask;
 
                 if (masked_msbs != 0 && masked_msbs != mask) {
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index a55d1566687..667d3b0a507 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -21,6 +21,7 @@ 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/module.h"
+#include "qemu/target_info.h"
 #include "system/reset.h"
 #include "system/qtest.h"
 #include "qemu/cutils.h"
@@ -72,7 +73,7 @@  static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val)
         ret = riscv_csrr(env, csrno, (target_ulong *)val);
     } else if (strcmp(cmd, "set_csr") == 0) {
         ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val,
-                MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
+                MAKE_64BIT_MASK(0, target_long_bits()));
     }
 
     g_assert(ret == RISCV_EXCP_NONE);