| Message ID | 20250402210328.52897-3-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: philmd's queue | expand |
diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h index 50c18bd326d..394c191da8d 100644 --- a/include/tcg/insn-start-words.h +++ b/include/tcg/insn-start-words.h @@ -8,10 +8,6 @@ #include "cpu.h" -#ifndef TARGET_INSN_START_EXTRA_WORDS -# define TARGET_INSN_START_WORDS 1 -#else # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) -#endif #endif /* TARGET_INSN_START_WORDS */ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index bc46b5570c4..cded92a4479 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -23,7 +23,7 @@ # error #endif -#ifndef TARGET_INSN_START_EXTRA_WORDS +#if TARGET_INSN_START_EXTRA_WORDS == 0 static inline void tcg_gen_insn_start(target_ulong pc) { TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS); diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index 63989e71c06..dd44feb1793 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -24,6 +24,8 @@ # define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) #endif +#define TARGET_INSN_START_EXTRA_WORDS 0 + /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index f5248ce9e79..9d37848d97d 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -25,6 +25,8 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #define TCG_GUEST_DEFAULT_MO 0 #endif diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 45ee7b46409..635d509e743 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -23,4 +23,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 36 #define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #endif diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index 52437946e56..dbe414bb35a 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -13,6 +13,8 @@ #define TARGET_PAGE_BITS 12 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #define TCG_GUEST_DEFAULT_MO (0) #endif diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index 553ad2f4c6a..d0651d2ac89 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -37,6 +37,8 @@ # define TARGET_PAGE_BITS 12 #endif +#define TARGET_INSN_START_EXTRA_WORDS 0 + #define TCG_GUEST_DEFAULT_MO 0 #endif diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index ef1970a09e9..84934f3bcaf 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -24,4 +24,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #endif diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index 790242ef3d2..eb33a67c419 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -12,4 +12,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #endif diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index 5e4848ad059..e7cb747aaae 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -16,6 +16,8 @@ #define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif +#define TARGET_INSN_START_EXTRA_WORDS 0 + /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0)