| Message ID | 20250327-videocc-pll-multi-pd-voting-v3-16-895fafd62627@quicinc.com |
|---|---|
| State | New |
| Headers | show
Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com
[205.220.168.131])
(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
(No client certificate requested)
by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BB7620D4F3;
Thu, 27 Mar 2025 09:55:01 +0000 (UTC)
Authentication-Results: smtp.subspace.kernel.org;
arc=none smtp.client-ip=205.220.168.131
ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
t=1743069302; cv=none;
b=Y+bV/Wivhwe3EwHh2kD7d6cbF6Bg6aY4UBo2Nxq3oq4kdA6uQ6DanERLF1EwZYRmm65i51umtZi8Sfo6bcvntWv2V0oc/xWRRv0JEtAYQ6Q9iM6kmKjDTw+Sbew9X91pyDNUM0bvFpWWpQpmR6FtgAKA0mmxTLcE9qykCV0/vpA=
ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org;
s=arc-20240116; t=1743069302; c=relaxed/simple;
bh=1fj6QxdkYv/WhfelCPDxoSPPmQnwUpaJSWoH5AB1iKQ=;
h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References:
In-Reply-To:To:CC;
b=jx8v9bFprQRGxX2ZLq+nFqQWRiydpdUSsNejHqzJJl3bjIk6A94IZ+i9Kd68F/zZrTFRxYP8udweYRuKxoI9LDcEYdyKzz02IoTwmRcw6bfZ/fVLkh1SjTOKPORU5qqnTPIxT7euzDyK/5qil3coY8pbQJEWqxdz/btUsVXAukM=
ARC-Authentication-Results: i=1; smtp.subspace.kernel.org;
dmarc=pass (p=none dis=none) header.from=quicinc.com;
spf=pass smtp.mailfrom=quicinc.com;
dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com
header.b=MgUEdAmJ; arc=none smtp.client-ip=205.220.168.131
Authentication-Results: smtp.subspace.kernel.org;
dmarc=pass (p=none dis=none) header.from=quicinc.com
Authentication-Results: smtp.subspace.kernel.org;
spf=pass smtp.mailfrom=quicinc.com
Authentication-Results: smtp.subspace.kernel.org;
dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com
header.b="MgUEdAmJ"
Received: from pps.filterd (m0279864.ppops.net [127.0.0.1])
by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id
52R5jF8J025693;
Thu, 27 Mar 2025 09:54:58 GMT
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=
cc:content-transfer-encoding:content-type:date:from:in-reply-to
:message-id:mime-version:references:subject:to; s=qcppdkim1; bh=
Cf7g0UazzorT3xzCO728Wsoim5pu4BVEfNVq7pRphac=; b=MgUEdAmJFq6iBFLm
/TxXT62b3BT8JtjH7YESVx6HDO7qnr8hWWKu650BDwjwrHnYkYmyzqoZX4N5P2R+
DISVKp0dh9iKMxB01e9IBgu/Y3/x1PDxYu8MVee5vi26x8FcxaoFYQFkqDh6evFO
XX/9OkZHdlJmqLpO1vFQIteK9/9/iNZc/OI0szrTu8iXNgUywOtxR6tnsLwoMtvf
GX/IzJp//lhYDOclKIGwcV3tLMWCiNk5F8dc7UO09I2LWJcLi1EyDFFr6pejh4nF
6lQMBa6FZ7NNVEgvQK0FiRCeNlJ4l2ABeVnb4DbsuUB7w4RCZ1QTQUuEzMyd0gmS
efwS/Q==
Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com
[129.46.96.20])
by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45n0nurnue-1
(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);
Thu, 27 Mar 2025 09:54:57 +0000 (GMT)
Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com
[10.47.209.196])
by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id
52R9svCU017624
(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);
Thu, 27 Mar 2025 09:54:57 GMT
Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com
(10.47.209.196) with Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 27 Mar
2025 02:54:51 -0700
From: Jagadeesh Kona <quic_jkona@quicinc.com>
Date: Thu, 27 Mar 2025 15:22:36 +0530
Subject: [PATCH v3 16/18] arm64: dts: qcom: Add MXC power domain to camcc
node on SM8450
Precedence: bulk
X-Mailing-List: linux-arm-msm@vger.kernel.org
List-Id: <linux-arm-msm.vger.kernel.org>
List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
Message-ID:
<20250327-videocc-pll-multi-pd-voting-v3-16-895fafd62627@quicinc.com>
References:
<20250327-videocc-pll-multi-pd-voting-v3-0-895fafd62627@quicinc.com>
In-Reply-To:
<20250327-videocc-pll-multi-pd-voting-v3-0-895fafd62627@quicinc.com>
To: Bjorn Andersson <andersson@kernel.org>,
Michael Turquette
<mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring
<robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley
<conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
"Vladimir
Zapolskiy" <vladimir.zapolskiy@linaro.org>,
Dmitry Baryshkov
<lumag@kernel.org>
CC: Ajit Pandey <quic_ajipan@quicinc.com>,
Imran Shaik
<quic_imrashai@quicinc.com>,
Taniya Das <quic_tdas@quicinc.com>,
"Satya Priya
Kakitapalli" <quic_skakitap@quicinc.com>,
<linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org>,
Jagadeesh Kona <quic_jkona@quicinc.com>,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
X-Mailer: b4 0.14.2
X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To
nalasex01a.na.qualcomm.com (10.47.209.196)
X-QCInternal: smtphost
X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800
signatures=585085
X-Proofpoint-GUID: WaNbk8uZ0vH4XWMzDY1zyhPsVHclE5s-
X-Authority-Analysis: v=2.4 cv=AcaxH2XG c=1 sm=1 tr=0 ts=67e52072 cx=c_pps
a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17
a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8
a=yDpTXWEf0LF08gPbhRgA:9 a=QEXdDO2ut3YA:10
a=TjNXssC_j7lpFel5tvFf:22
X-Proofpoint-ORIG-GUID: WaNbk8uZ0vH4XWMzDY1zyhPsVHclE5s-
X-Proofpoint-Virus-Version: vendor=baseguard
engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34
definitions=2025-03-26_09,2025-03-26_02,2024-11-22_01
X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0
clxscore=1015 mlxlogscore=725
impostorscore=0 malwarescore=0 bulkscore=0 mlxscore=0 adultscore=0
phishscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0
suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc=
route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000
definitions=main-2503270066
|
| Series |
clk: qcom: Add support to attach multiple power domains in cc probe
|
expand
|
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 36a67c679fbaed944d7590528b696635c306da5d..624190c07c59f3e6714f296f1b264d2a88135116 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3292,8 +3292,10 @@ camcc: clock-controller@ade0000 { <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;
Camcc requires both MMCX and MXC rails to be powered ON to configure the camera PLLs on SM8450 platform. Hence add MXC power domain to camcc node on SM8450. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)