| Message ID | 20250323123333.1622860-1-quic_nkumarsi@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v4] arm64: dts: qcom: Add industrial mezzanine support for qcs6490-rb3gen2 | expand |
On Sun, Mar 23, 2025 at 06:03:33PM +0530, Nirmesh Kumar Singh wrote: > Add DTS support for Qualcomm qcs6490-rb3gen2 industrial mezzanine board. > > Signed-off-by: Sahil Chandna <quic_chandna@quicinc.com> > Signed-off-by: Nirmesh Kumar Singh <quic_nkumarsi@quicinc.com> > > --- > Changes in v4: > - Fixed the GPIO state setting using hardware rework instead of the > pinctrl framework, based on Dmitry's comment. This looks really nice! Thank you for sharing the DT early enough so that it was possible to fix it! > - Link to V3: https://lore.kernel.org/all/20250122101424.1810844-1-quic_nkumarsi@quicinc.com/ > > Changes in v3: > - Fixed tpm pinctrl node label. > - Addressed comments by Dmitry. > - Improved indentation/formatting. > - Link to V2: https://lore.kernel.org/all/20250102190155.2593453-1-quic_nkumarsi@quicinc.com/ > > Changes in V2: > - Addressed comment by Konrad. > - Validated dts bindings with dtb_checks suggested by Krzysztof. > - Improved indentation/formatting. > - Fixed bug encountered during testing. > - Added dtb entry in makefile. > - Link to V1: https://lore.kernel.org/all/20241206065156.2573-1-quic_chandna@quicinc.com/ > --- > --- > arch/arm64/boot/dts/qcom/Makefile | 4 ++++ > .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 21 +++++++++++++++++++ > 2 files changed, 25 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 140b0b2abfb5..625b47d94416 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -116,6 +116,10 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb + +qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-industrial-mezzanine.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso new file mode 100644 index 000000000000..619a42b5ef48 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. +*/ + +/dts-v1/; +/plugin/; +#include <dt-bindings/clock/qcom,gcc-sc7280.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +&spi11 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + st33htpm0: tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +};