| Message ID | 20250321-qcom_ipq5424_cmnpll-v1-4-3ea8e5262da4@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add CMN PLL clock controller support for IPQ5424 | expand |
diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index b4d1aa00c944..e503b6677a3e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -224,8 +224,13 @@ &ref_48mhz_clk { clock-mult = <1>; }; +/* + * The frequency of xo_board is fixed to 24 MHZ, which is routed + * from WiFi output clock 48 MHZ divided by 2. + */ &xo_board { - clock-frequency = <24000000>; + clock-div = <2>; + clock-mult = <1>; }; &xo_clk { diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 844788990f43..6974339c126f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -30,7 +30,8 @@ sleep_clk: sleep-clk { }; xo_board: xo-board-clk { - compatible = "fixed-clock"; + compatible = "fixed-factor-clock"; + clocks = <&ref_48mhz_clk>; #clock-cells = <0>; };
xo_board is fixed to 24 MHZ, which is routed from WiFi output clock 48 MHZ (also being the reference clock of CMN PLL) divided 2 by analog block routing channel. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 7 ++++++- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-)