| Message ID | 20250321135854.1431375-3-ivo.ivanov.ivanov1@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | phy: samsung: add Exynos2200 SNPS eUSB2 driver | expand |
On Fri, Mar 21, 2025 at 03:58:46PM +0200, Ivaylo Ivanov wrote: > Document support for Exynos2200. As the USBDRD 3.2 4nm controller > consists of Synopsys eUSB2.0 phy and USBDP/SS combophy, which will > be handled by external drivers, define only the bus clocked used > by the link controller. > > Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > --- > .../bindings/phy/samsung,usb3-drd-phy.yaml | 38 +++++++++++++++++-- > 1 file changed, 34 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml > index 16321cdd4..819e4afe6 100644 > --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml > @@ -26,6 +26,7 @@ properties: > compatible: > enum: > - google,gs101-usb31drd-phy > + - samsung,exynos2200-usb32drd-phy > - samsung,exynos5250-usbdrd-phy > - samsung,exynos5420-usbdrd-phy > - samsung,exynos5433-usbdrd-phy > @@ -33,24 +34,32 @@ properties: > - samsung,exynos850-usbdrd-phy > > clocks: > - minItems: 2 > + minItems: 1 > maxItems: 5 > > clock-names: > - minItems: 2 > + minItems: 1 > maxItems: 5 > description: | > - At least two clocks:: > + Typically two clocks:: Don't need double colon. > - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used > for register access. > - PHY reference clock (usually crystal clock), used for PHY operations, > associated by phy name. It is used to determine bit values for clock > settings register. For Exynos5420 this is given as 'sclk_usbphy30' > - in the CMU. > + in the CMU. It's not needed for Exynos2200. > > "#phy-cells": > const: 1 > > + phys: > + maxItems: 1 > + description: > + Phandle to USBDRD-underlying high-speed PHY Drop 'phandle to'. > + > + phy-names: > + const: hs > + > port: > $ref: /schemas/graph.yaml#/properties/port > description: > @@ -137,6 +146,27 @@ allOf: > - vdda-usbdp-supply > - vddh-usbdp-supply > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - samsung,exynos2200-usb32drd-phy > + then: > + properties: > + clocks: > + maxItems: 1 > + clock-names: > + items: > + - const: phy > + reg: > + maxItems: 1 > + reg-names: > + maxItems: 1 > + required: > + - phys > + - phy-names > + > - if: > properties: > compatible: > -- > 2.43.0 >
diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 16321cdd4..819e4afe6 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -26,6 +26,7 @@ properties: compatible: enum: - google,gs101-usb31drd-phy + - samsung,exynos2200-usb32drd-phy - samsung,exynos5250-usbdrd-phy - samsung,exynos5420-usbdrd-phy - samsung,exynos5433-usbdrd-phy @@ -33,24 +34,32 @@ properties: - samsung,exynos850-usbdrd-phy clocks: - minItems: 2 + minItems: 1 maxItems: 5 clock-names: - minItems: 2 + minItems: 1 maxItems: 5 description: | - At least two clocks:: + Typically two clocks:: - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used for register access. - PHY reference clock (usually crystal clock), used for PHY operations, associated by phy name. It is used to determine bit values for clock settings register. For Exynos5420 this is given as 'sclk_usbphy30' - in the CMU. + in the CMU. It's not needed for Exynos2200. "#phy-cells": const: 1 + phys: + maxItems: 1 + description: + Phandle to USBDRD-underlying high-speed PHY + + phy-names: + const: hs + port: $ref: /schemas/graph.yaml#/properties/port description: @@ -137,6 +146,27 @@ allOf: - vdda-usbdp-supply - vddh-usbdp-supply + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos2200-usb32drd-phy + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: phy + reg: + maxItems: 1 + reg-names: + maxItems: 1 + required: + - phys + - phy-names + - if: properties: compatible:
Document support for Exynos2200. As the USBDRD 3.2 4nm controller consists of Synopsys eUSB2.0 phy and USBDP/SS combophy, which will be handled by external drivers, define only the bus clocked used by the link controller. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> --- .../bindings/phy/samsung,usb3-drd-phy.yaml | 38 +++++++++++++++++-- 1 file changed, 34 insertions(+), 4 deletions(-)