diff mbox series

[PATCH-for-10.1,1/4] target/riscv: Restrict RV128 MTTCG check on system emulation

Message ID 20250321155925.96626-2-philmd@linaro.org
State Superseded
Headers show
Series tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field | expand

Commit Message

Philippe Mathieu-Daudé March 21, 2025, 3:59 p.m. UTC 
Multi-threaded TCG only concerns system emulation.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/tcg/tcg-cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Pierrick Bouvier March 21, 2025, 5:32 p.m. UTC | #1 
On 3/21/25 08:59, Philippe Mathieu-Daudé wrote:
> Multi-threaded TCG only concerns system emulation.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/riscv/tcg/tcg-cpu.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index fb903992faa..60a26acc503 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -1050,6 +1050,7 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
>           return false;
>       }
>   
> +#ifndef CONFIG_USER_ONLY
>       if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
>           /* Missing 128-bit aligned atomics */
>           error_setg(errp,
> @@ -1058,7 +1059,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
>           return false;
>       }
>   
> -#ifndef CONFIG_USER_ONLY
>       CPURISCVState *env = &cpu->env;
>   
>       tcg_cflags_set(CPU(cs), CF_PCREL);

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff mbox series

Patch

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index fb903992faa..60a26acc503 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1050,6 +1050,7 @@  static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
         return false;
     }
 
+#ifndef CONFIG_USER_ONLY
     if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
         /* Missing 128-bit aligned atomics */
         error_setg(errp,
@@ -1058,7 +1059,6 @@  static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
         return false;
     }
 
-#ifndef CONFIG_USER_ONLY
     CPURISCVState *env = &cpu->env;
 
     tcg_cflags_set(CPU(cs), CF_PCREL);