[PULL,23/23] accel/tcg: Build tcg-runtime-gvec.c once

Message ID	20250308225902.1208237-25-richard.henderson@linaro.org
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Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>, Pierrick Bouvier <pierrick.bouvier@linaro.org> Subject: [PULL 23/23] accel/tcg: Build tcg-runtime-gvec.c once Date: Sat, 8 Mar 2025 14:59:02 -0800 Message-ID: <20250308225902.1208237-25-richard.henderson@linaro.org> In-Reply-To: <20250308225902.1208237-1-richard.henderson@linaro.org> References: <20250308225902.1208237-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[v2] linux-user/riscv: Fix handling of cpu mask in riscv_hwprobe syscall \| expand [v2] linux-user/riscv: Fix handling of cpu mask in riscv_hwprobe syscall [PULL,02/23] accel/tcg: Restrict CPU_TLB_DYN__BITS definitions to accel/tcg/ [PULL,03/23] include/exec: Move TARGET_PAGE_{SIZE, MASK, BITS} to target_page.h [PULL,04/23] include/exec: Split out exec/cpu-interrupt.h [PULL,05/23] accel/tcg: Compile watchpoint.c once [PULL,06/23] exec: Declare tlb_reset_dirty() in 'exec/cputlb.h' [PULL,07/23] exec: Declare tlb_set_page_full() in 'exec/cputlb.h' [PULL,08/23] exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h' [PULL,09/23] exec: Declare tlb_set_page() in 'exec/cputlb.h' [PULL,10/23] exec: Declare tlb_hit() in 'exec/cputlb.h' [PULL,11/23] exec: Declare tlb_flush() in 'exec/cputlb.h' [PULL,12/23] system: Build watchpoint.c once [PULL,13/23] accel/tcg: Build tcg-accel-ops.c once [PULL,14/23] accel/tcg: Build tcg-accel-ops-icount.c once [PULL,15/23] accel/tcg: Build tcg-accel-ops-rr.c once [PULL,16/23] accel/tcg: Build tcg-accel-ops-mttcg.c once [PULL,17/23] accel/tcg: Restrict GETPC_ADJ to 'tb-internal.h' [PULL,18/23] accel/tcg: Split out getpc.h [PULL,19/23] qemu/atomic: Rename atomic128-cas.h headers using .h.inc suffix [PULL,20/23] qemu/atomic: Rename atomic128-ldst.h headers using .h.inc suffix [PULL,21/23] qemu/atomic128: Include missing 'qemu/atomic.h' header [PULL,22/23] accel/tcg: Build tcg-runtime.c once [PULL,23/23] accel/tcg: Build tcg-runtime-gvec.c once

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Subject: [PULL 23/23] accel/tcg: Build tcg-runtime-gvec.c once
Date: Sat,  8 Mar 2025 14:59:02 -0800
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Series

[v2] linux-user/riscv: Fix handling of cpu mask in riscv_hwprobe syscall | expand

Commit Message

Richard Henderson March 8, 2025, 10:59 p.m. UTC

Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/tcg-runtime-gvec.c | 1 -
 accel/tcg/meson.build        | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index afca89baa1..ff927c5dd8 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -19,7 +19,6 @@ 
 
 #include "qemu/osdep.h"
 #include "qemu/host-utils.h"
-#include "cpu.h"
 #include "exec/helper-proto-common.h"
 #include "tcg/tcg-gvec-desc.h"
 
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index 411fe28dea..38ff227eb0 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -1,13 +1,13 @@ 
 common_ss.add(when: 'CONFIG_TCG', if_true: files(
   'cpu-exec-common.c',
   'tcg-runtime.c',
+  'tcg-runtime-gvec.c',
 ))
 tcg_specific_ss = ss.source_set()
 tcg_specific_ss.add(files(
   'tcg-all.c',
   'cpu-exec.c',
   'tb-maint.c',
-  'tcg-runtime-gvec.c',
   'translate-all.c',
   'translator.c',
 ))

[PULL,23/23] accel/tcg: Build tcg-runtime-gvec.c once

Commit Message

Patch