| Message ID | 20250308213640.13138-14-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | hw/sd/sdhci: Set reset value of interrupt registers | expand |
On Sat, 8 Mar 2025, Philippe Mathieu-Daudé wrote: > Per the MPC8569E reference manual, its SDHC I/O range is 4KiB > wide, mapped in big endian order, and it only accepts 32-bit > aligned access. Set the default register reset values. > > Reported-by: BALATON Zoltan <balaton@eik.bme.hu> > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > include/hw/sd/sdhci.h | 2 ++ > hw/sd/sdhci.c | 37 ++++++++++++++++++++++++++++++++++++- > 2 files changed, 38 insertions(+), 1 deletion(-) > > diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h > index eb8380187b5..966a1751f50 100644 > --- a/include/hw/sd/sdhci.h > +++ b/include/hw/sd/sdhci.h > @@ -162,6 +162,8 @@ DECLARE_INSTANCE_CHECKER(SDHCIState, SYSBUS_SDHCI, > DECLARE_CLASS_CHECKERS(SDHCIClass, SYSBUS_SDHCI, > TYPE_SYSBUS_SDHCI) > > +#define TYPE_FSL_ESDHC "fsl-esdhc" > + > #define TYPE_IMX_USDHC "imx-usdhc" > > #define TYPE_S3C_SDHCI "s3c-sdhci" > diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c > index 234a6e4a1fe..d5cc0bf1458 100644 > --- a/hw/sd/sdhci.c > +++ b/hw/sd/sdhci.c > @@ -1653,7 +1653,37 @@ static void sdhci_bus_class_init(ObjectClass *klass, void *data) > sbc->set_readonly = sdhci_set_readonly; > } > > -/* --- qdev i.MX eSDHC --- */ > +/* --- Freescale eSDHC (MPC8569ERM Rev.2 from 06/2011) --- */ > + > +static const MemoryRegionOps fsl_esdhc_mmio_ops = { > + .read = sdhci_read, > + .write = sdhci_write, > + .valid = { > + .min_access_size = 4, Does this need max access too? Maybe it could work with 8 and likely nothing would try to access more than 4 so probably does not matter. Regards, BALATON Zoltan > + .unaligned = false > + }, > + .endianness = DEVICE_BIG_ENDIAN, > +}; > + > +static void fsl_esdhc_class_init(ObjectClass *oc, void *data) > +{ > + SDHCIClass *sc = SYSBUS_SDHCI_CLASS(oc); > + > + sc->iomem_size = 0x1000; > + sc->io_ops = &fsl_esdhc_mmio_ops; > + sc->ro.capareg = 0x01e30000; > + sc->reset.sdmasysad = 8; > + sc->reset.blkcnt = 8; > + sc->reset.prnsts = 0xff800000; > + sc->reset.hostctl1 = 0x20; /* Endian mode (address-invariant) */ > + sc->reset.clkcon = 0x8000; > + sc->reset.norintstsen = 0x013f; > + sc->reset.errintstsen = 0x117f; > + > + sdhci_common_class_init(oc, data); > +} > + > +/* --- qdev i.MX uSDHC --- */ > > #define USDHC_MIX_CTRL 0x48 > > @@ -1983,6 +2013,11 @@ static const TypeInfo sdhci_types[] = { > .class_size = sizeof(SDHCIClass), > .class_init = sdhci_sysbus_class_init, > }, > + { > + .name = TYPE_FSL_ESDHC, > + .parent = TYPE_SYSBUS_SDHCI, > + .class_init = fsl_esdhc_class_init, > + }, > { > .name = TYPE_IMX_USDHC, > .parent = TYPE_SYSBUS_SDHCI, >
On 9/3/25 12:04, BALATON Zoltan wrote: > On Sat, 8 Mar 2025, Philippe Mathieu-Daudé wrote: >> Per the MPC8569E reference manual, its SDHC I/O range is 4KiB >> wide, mapped in big endian order, and it only accepts 32-bit >> aligned access. Set the default register reset values. >> >> Reported-by: BALATON Zoltan <balaton@eik.bme.hu> >> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> --- >> include/hw/sd/sdhci.h | 2 ++ >> hw/sd/sdhci.c | 37 ++++++++++++++++++++++++++++++++++++- >> 2 files changed, 38 insertions(+), 1 deletion(-) >> -/* --- qdev i.MX eSDHC --- */ >> +/* --- Freescale eSDHC (MPC8569ERM Rev.2 from 06/2011) --- */ >> + >> +static const MemoryRegionOps fsl_esdhc_mmio_ops = { >> + .read = sdhci_read, >> + .write = sdhci_write, >> + .valid = { >> + .min_access_size = 4, > > Does this need max access too? Maybe it could work with 8 and likely > nothing would try to access more than 4 so probably does not matter. Per the reference manual (chapter 16): All eSDHC registers must be accessed as aligned 4-byte quantities. Accesses to the eSDHC registers that are less than 4-bytes are not supported. There is no precision on max_access_size. > Regards, > BALATON Zoltan
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index eb8380187b5..966a1751f50 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -162,6 +162,8 @@ DECLARE_INSTANCE_CHECKER(SDHCIState, SYSBUS_SDHCI, DECLARE_CLASS_CHECKERS(SDHCIClass, SYSBUS_SDHCI, TYPE_SYSBUS_SDHCI) +#define TYPE_FSL_ESDHC "fsl-esdhc" + #define TYPE_IMX_USDHC "imx-usdhc" #define TYPE_S3C_SDHCI "s3c-sdhci" diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 234a6e4a1fe..d5cc0bf1458 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1653,7 +1653,37 @@ static void sdhci_bus_class_init(ObjectClass *klass, void *data) sbc->set_readonly = sdhci_set_readonly; } -/* --- qdev i.MX eSDHC --- */ +/* --- Freescale eSDHC (MPC8569ERM Rev.2 from 06/2011) --- */ + +static const MemoryRegionOps fsl_esdhc_mmio_ops = { + .read = sdhci_read, + .write = sdhci_write, + .valid = { + .min_access_size = 4, + .unaligned = false + }, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void fsl_esdhc_class_init(ObjectClass *oc, void *data) +{ + SDHCIClass *sc = SYSBUS_SDHCI_CLASS(oc); + + sc->iomem_size = 0x1000; + sc->io_ops = &fsl_esdhc_mmio_ops; + sc->ro.capareg = 0x01e30000; + sc->reset.sdmasysad = 8; + sc->reset.blkcnt = 8; + sc->reset.prnsts = 0xff800000; + sc->reset.hostctl1 = 0x20; /* Endian mode (address-invariant) */ + sc->reset.clkcon = 0x8000; + sc->reset.norintstsen = 0x013f; + sc->reset.errintstsen = 0x117f; + + sdhci_common_class_init(oc, data); +} + +/* --- qdev i.MX uSDHC --- */ #define USDHC_MIX_CTRL 0x48 @@ -1983,6 +2013,11 @@ static const TypeInfo sdhci_types[] = { .class_size = sizeof(SDHCIClass), .class_init = sdhci_sysbus_class_init, }, + { + .name = TYPE_FSL_ESDHC, + .parent = TYPE_SYSBUS_SDHCI, + .class_init = fsl_esdhc_class_init, + }, { .name = TYPE_IMX_USDHC, .parent = TYPE_SYSBUS_SDHCI,
Per the MPC8569E reference manual, its SDHC I/O range is 4KiB wide, mapped in big endian order, and it only accepts 32-bit aligned access. Set the default register reset values. Reported-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- include/hw/sd/sdhci.h | 2 ++ hw/sd/sdhci.c | 37 ++++++++++++++++++++++++++++++++++++- 2 files changed, 38 insertions(+), 1 deletion(-)