| Message ID | 20250305-dra-v1-1-8dc6d9a0e1c0@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: dra7xx: Try to clean up dra7xx_pcie_cpu_addr_fixup() | expand |
On Wed, Mar 05, 2025 at 11:20:22AM -0500, Frank Li wrote: If you want a specific patch to be tested, you can add [PATCH RFT] tag.C > According to code in drivers/pci/controller/dwc/pci-dra7xx.c > > dra7xx_pcie_cpu_addr_fixup() > { > return cpu_addr & DRA7XX_CPU_TO_BUS_ADDR; //0x0FFFFFFF > } > > PCI parent bus trim high 4 bits address to 0. Correct ranges in > target-module@51000000 to algin hardware behavior, which translate PCIe > outbound address 0..0x0fff_ffff to 0x2000_0000..0x2fff_ffff. > > Set 'config' and 'addr_space' reg values to 0. > Change parent bus address of downstream I/O and non-prefetchable memory to > 0. > > Ensure no functional impact on the final address translation result. > > Prepare for the removal of the driver’s cpu_addr_fixup(). > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > arch/arm/boot/dts/ti/omap/dra7.dtsi | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/arch/arm/boot/dts/ti/omap/dra7.dtsi b/arch/arm/boot/dts/ti/omap/dra7.dtsi > index b709703f6c0d4..9213fdd25330b 100644 > --- a/arch/arm/boot/dts/ti/omap/dra7.dtsi > +++ b/arch/arm/boot/dts/ti/omap/dra7.dtsi > @@ -196,7 +196,7 @@ axi0: target-module@51000000 { > #size-cells = <1>; > #address-cells = <1>; > ranges = <0x51000000 0x51000000 0x3000>, > - <0x20000000 0x20000000 0x10000000>; > + <0x00000000 0x20000000 0x10000000>; I'm not able to interpret this properly. So this essentially means that the parent address 0x20000000 is mapped to child address 0x00000000. And the child address is same for other controller as well. Also, the cpu_addr_fixup() is doing the same by masking out the upper 4 bits. I tried looking into the DRA7 TRM, but it says (ECAM_Param_Base_Addr + 0x20000000) where ECAM_Param_Base_Addr = 0x0000_0000 to 0x0FFF_F000. I couldn't relate TRM with the cpu_addr_fixup() callback. Can someone from TI shed light on this? - Mani
diff --git a/arch/arm/boot/dts/ti/omap/dra7.dtsi b/arch/arm/boot/dts/ti/omap/dra7.dtsi index b709703f6c0d4..9213fdd25330b 100644 --- a/arch/arm/boot/dts/ti/omap/dra7.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7.dtsi @@ -196,7 +196,7 @@ axi0: target-module@51000000 { #size-cells = <1>; #address-cells = <1>; ranges = <0x51000000 0x51000000 0x3000>, - <0x20000000 0x20000000 0x10000000>; + <0x00000000 0x20000000 0x10000000>; dma-ranges; /** * To enable PCI endpoint mode, disable the pcie1_rc @@ -205,14 +205,14 @@ axi0: target-module@51000000 { pcie1_rc: pcie@51000000 { reg = <0x51000000 0x2000>, <0x51002000 0x14c>, - <0x20001000 0x2000>; + <0x00001000 0x2000>; reg-names = "rc_dbics", "ti_conf", "config"; interrupts = <0 232 0x4>, <0 233 0x4>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>, - <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>; + ranges = <0x81000000 0 0x00000000 0x00003000 0 0x00010000>, + <0x82000000 0 0x20013000 0x00013000 0 0x0ffed000>; bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; @@ -238,7 +238,7 @@ pcie1_ep: pcie_ep@51000000 { reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, - <0x20001000 0x10000000>; + <0x00001000 0x10000000>; reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; interrupts = <0 232 0x4>; num-lanes = <1>; @@ -270,20 +270,20 @@ axi1: target-module@51800000 { #size-cells = <1>; #address-cells = <1>; ranges = <0x51800000 0x51800000 0x3000>, - <0x30000000 0x30000000 0x10000000>; + <0x00000000 0x30000000 0x10000000>; dma-ranges; status = "disabled"; pcie2_rc: pcie@51800000 { reg = <0x51800000 0x2000>, <0x51802000 0x14c>, - <0x30001000 0x2000>; + <0x00001000 0x2000>; reg-names = "rc_dbics", "ti_conf", "config"; interrupts = <0 355 0x4>, <0 356 0x4>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>, - <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>; + ranges = <0x81000000 0 0x00000000 0x00003000 0 0x00010000>, + <0x82000000 0 0x30013000 0x00013000 0 0x0ffed000>; bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>;
According to code in drivers/pci/controller/dwc/pci-dra7xx.c dra7xx_pcie_cpu_addr_fixup() { return cpu_addr & DRA7XX_CPU_TO_BUS_ADDR; //0x0FFFFFFF } PCI parent bus trim high 4 bits address to 0. Correct ranges in target-module@51000000 to algin hardware behavior, which translate PCIe outbound address 0..0x0fff_ffff to 0x2000_0000..0x2fff_ffff. Set 'config' and 'addr_space' reg values to 0. Change parent bus address of downstream I/O and non-prefetchable memory to 0. Ensure no functional impact on the final address translation result. Prepare for the removal of the driver’s cpu_addr_fixup(). Signed-off-by: Frank Li <Frank.Li@nxp.com> --- arch/arm/boot/dts/ti/omap/dra7.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)