| Message ID | 20250226220414.343659-7-peter.griffin@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | ufs-exynos fixes for gs101 | expand |
On 2/26/25 2:04 PM, Peter Griffin wrote: > GPIO_OUT[0] is connected to the reset pin of embedded UFS device. > Before powering off the phy assert the reset signal. Does the above apply to the GS implementation only or does it apply to all SoC's with an Exynos UFS host controller? Thanks, Bart.
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 4c3e03a3b8d9..64e2bf924213 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -1517,6 +1517,7 @@ static void exynos_ufs_exit(struct ufs_hba *hba) { struct exynos_ufs *ufs = ufshcd_get_variant(hba); + hci_writel(ufs, 0 << 0, HCI_GPIO_OUT); phy_power_off(ufs->phy); phy_exit(ufs->phy); } @@ -1700,6 +1701,8 @@ static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, if (status == PRE_CHANGE) return 0; + hci_writel(ufs, 0 << 0, HCI_GPIO_OUT); + if (!ufshcd_is_link_active(hba)) phy_power_off(ufs->phy);
GPIO_OUT[0] is connected to the reset pin of embedded UFS device. Before powering off the phy assert the reset signal. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> --- drivers/ufs/host/ufs-exynos.c | 3 +++ 1 file changed, 3 insertions(+)