| Message ID | 20250224113742.2829545-2-quic_mdalam@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v1,1/3] arm64: dts: qcom: ipq9574: Add SPI nand support | expand |
On 2/25/2025 2:06 AM, Konrad Dybcio wrote: > On 24.02.2025 12:37 PM, Md Sadre Alam wrote: >> Add SPI NAND support for ipq9574 SoC. >> >> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> >> --- >> * Moved changes in ipq9574-rdp-common.dtsi to separate patch >> >> * Prefixed zero for reg address in qpic_bam and qpic_nand >> >> * For full change history, please refer to https://lore.kernel.org/linux-arm-msm/20241120091507.1404368-8-quic_mdalam@quicinc.com/ >> --- >> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 28 +++++++++++++++++++++++++++ >> 1 file changed, 28 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> index 942290028972..acbcf507adef 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -447,6 +447,34 @@ tcsr: syscon@1937000 { >> reg = <0x01937000 0x21000>; >> }; >> >> + qpic_bam: dma-controller@7984000 { >> + compatible = "qcom,bam-v1.7.0"; > > v1.7.4 Ok > >> + reg = <0x07984000 0x1c000>; >> + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QPIC_AHB_CLK>; >> + clock-names = "bam_clk"; >> + #dma-cells = <1>; >> + qcom,ee = <0>; >> + status = "disabled"; >> + }; >> + >> + qpic_nand: spi@79b0000 { >> + compatible = "qcom,ipq9574-snand"; >> + reg = <0x079b0000 0x10000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + clocks = <&gcc GCC_QPIC_CLK>, >> + <&gcc GCC_QPIC_AHB_CLK>, >> + <&gcc GCC_QPIC_IO_MACRO_CLK>; >> + clock-names = "core", "aon", "iom"; >> + dmas = <&qpic_bam 0>, >> + <&qpic_bam 1>, >> + <&qpic_bam 2>; >> + dma-names = "tx", "rx", "cmd"; > > Please make clock-names & dma-names a vertical list, like clocks and dmas > and shift the nodes so that they're sorted by address Ok, will fix and post in next revision. > > Konrad
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 942290028972..acbcf507adef 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -447,6 +447,34 @@ tcsr: syscon@1937000 { reg = <0x01937000 0x21000>; }; + qpic_bam: dma-controller@7984000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07984000 0x1c000>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible = "qcom,ipq9574-snand"; + reg = <0x079b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", "aon", "iom"; + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + }; + + sdhc_1: mmc@7804000 { compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>,
Add SPI NAND support for ipq9574 SoC. Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> --- * Moved changes in ipq9574-rdp-common.dtsi to separate patch * Prefixed zero for reg address in qpic_bam and qpic_nand * For full change history, please refer to https://lore.kernel.org/linux-arm-msm/20241120091507.1404368-8-quic_mdalam@quicinc.com/ --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 28 +++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)