| Message ID | 20250221-b4-sm8750-display-v3-18-3ea95b1630ea@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | drm/msm: Add support for SM8750 | expand |
On Fri, Feb 21, 2025 at 04:24:28PM +0100, Krzysztof Kozlowski wrote: > v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register > differences and new implementations of setup_alpha_out, > setup_border_color and so one for this. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- > > Changes in v3: > 1. New patch, split from previous big DPU v12.0. > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 20 +++++--- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 84 +++++++++++++++++++++++++++++-- > 2 files changed, 94 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > index b9fe3a7343d54f6f8b5aad7982928d5fc728bd61..7a35939ece180c15898b2eaa2f1f451767c741ae 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > @@ -319,15 +319,21 @@ static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc, > return true; > } > > -static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, > - struct dpu_plane_state *pstate, const struct msm_format *format) > +static void _dpu_crtc_setup_blend_cfg(const struct dpu_hw_ctl *ctl, > + struct dpu_crtc_mixer *mixer, > + struct dpu_plane_state *pstate, > + const struct msm_format *format) > { > struct dpu_hw_mixer *lm = mixer->hw_lm; > uint32_t blend_op; > - uint32_t fg_alpha, bg_alpha; > + uint32_t fg_alpha, bg_alpha, max_alpha; > > fg_alpha = pstate->base.alpha >> 8; > - bg_alpha = 0xff - fg_alpha; > + if (ctl->mdss_ver->core_major_ver < 12) > + max_alpha = 0xff; > + else > + max_alpha = 0x3ff; So, CTL is passed only to get struct dpu_mdss_version? It can either be passed directly or fetched via dpu_kms->catalog->mdss_ver > + bg_alpha = max_alpha - fg_alpha; > > /* default to opaque blending */ > if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE || > @@ -337,7 +343,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, > } else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { > blend_op = DPU_BLEND_FG_ALPHA_FG_CONST | > DPU_BLEND_BG_ALPHA_FG_PIXEL; > - if (fg_alpha != 0xff) { > + if (fg_alpha != max_alpha) { > bg_alpha = fg_alpha; > blend_op |= DPU_BLEND_BG_MOD_ALPHA | > DPU_BLEND_BG_INV_MOD_ALPHA; > @@ -348,7 +354,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, > /* coverage blending */ > blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL | > DPU_BLEND_BG_ALPHA_FG_PIXEL; > - if (fg_alpha != 0xff) { > + if (fg_alpha != max_alpha) { > bg_alpha = fg_alpha; > blend_op |= DPU_BLEND_FG_MOD_ALPHA | > DPU_BLEND_FG_INV_MOD_ALPHA | > @@ -482,7 +488,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, > > /* blend config update */ > for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) { > - _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format); > + _dpu_crtc_setup_blend_cfg(ctl, mixer + lm_idx, pstate, format); > > if (bg_alpha_enable && !format->alpha_enable) > mixer[lm_idx].mixer_op_mode = 0; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c > index 3bfb61cb83672dca4236bdbbbfb1e442223576d2..75bf3521b03c8e243ccfe1fc226aa71f23b296df 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c > @@ -19,12 +19,20 @@ > > /* These register are offset to mixer base + stage base */ > #define LM_BLEND0_OP 0x00 > + > +/* <v12 DPU with offset to mixer base + stage base */ > #define LM_BLEND0_CONST_ALPHA 0x04 > #define LM_FG_COLOR_FILL_COLOR_0 0x08 > #define LM_FG_COLOR_FILL_COLOR_1 0x0C lowercase hex > #define LM_FG_COLOR_FILL_SIZE 0x10 > #define LM_FG_COLOR_FILL_XY 0x14 > > +/* >= v12 DPU */ > +#define LM_BORDER_COLOR_0_V12 0x1C lowercase hex > +#define LM_BORDER_COLOR_1_V12 0x20 > + > +/* >= v12 DPU with offset to mixer base + stage base */ > +#define LM_BLEND0_CONST_ALPHA_V12 0x08 This doesn't seem to be aligned properly > #define LM_BLEND0_FG_ALPHA 0x04 > #define LM_BLEND0_BG_ALPHA 0x08 >
On 21/02/2025 17:25, Dmitry Baryshkov wrote: >> -static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, >> - struct dpu_plane_state *pstate, const struct msm_format *format) >> +static void _dpu_crtc_setup_blend_cfg(const struct dpu_hw_ctl *ctl, >> + struct dpu_crtc_mixer *mixer, >> + struct dpu_plane_state *pstate, >> + const struct msm_format *format) >> { >> struct dpu_hw_mixer *lm = mixer->hw_lm; >> uint32_t blend_op; >> - uint32_t fg_alpha, bg_alpha; >> + uint32_t fg_alpha, bg_alpha, max_alpha; >> >> fg_alpha = pstate->base.alpha >> 8; >> - bg_alpha = 0xff - fg_alpha; >> + if (ctl->mdss_ver->core_major_ver < 12) >> + max_alpha = 0xff; >> + else >> + max_alpha = 0x3ff; > > So, CTL is passed only to get struct dpu_mdss_version? It can either be > passed directly or fetched via dpu_kms->catalog->mdss_ver Ack. > >> + bg_alpha = max_alpha - fg_alpha; >> >> /* default to opaque blending */ >> if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE || >> @@ -337,7 +343,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, >> } else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { >> blend_op = DPU_BLEND_FG_ALPHA_FG_CONST | >> DPU_BLEND_BG_ALPHA_FG_PIXEL; >> - if (fg_alpha != 0xff) { >> + if (fg_alpha != max_alpha) { >> bg_alpha = fg_alpha; >> blend_op |= DPU_BLEND_BG_MOD_ALPHA | >> DPU_BLEND_BG_INV_MOD_ALPHA; >> @@ -348,7 +354,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, >> /* coverage blending */ >> blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL | >> DPU_BLEND_BG_ALPHA_FG_PIXEL; >> - if (fg_alpha != 0xff) { >> + if (fg_alpha != max_alpha) { >> bg_alpha = fg_alpha; >> blend_op |= DPU_BLEND_FG_MOD_ALPHA | >> DPU_BLEND_FG_INV_MOD_ALPHA | >> @@ -482,7 +488,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, >> >> /* blend config update */ >> for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) { >> - _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format); >> + _dpu_crtc_setup_blend_cfg(ctl, mixer + lm_idx, pstate, format); >> >> if (bg_alpha_enable && !format->alpha_enable) >> mixer[lm_idx].mixer_op_mode = 0; >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c >> index 3bfb61cb83672dca4236bdbbbfb1e442223576d2..75bf3521b03c8e243ccfe1fc226aa71f23b296df 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c >> @@ -19,12 +19,20 @@ >> >> /* These register are offset to mixer base + stage base */ >> #define LM_BLEND0_OP 0x00 >> + >> +/* <v12 DPU with offset to mixer base + stage base */ >> #define LM_BLEND0_CONST_ALPHA 0x04 >> #define LM_FG_COLOR_FILL_COLOR_0 0x08 >> #define LM_FG_COLOR_FILL_COLOR_1 0x0C > > lowercase hex Ack > >> #define LM_FG_COLOR_FILL_SIZE 0x10 >> #define LM_FG_COLOR_FILL_XY 0x14 >> >> +/* >= v12 DPU */ >> +#define LM_BORDER_COLOR_0_V12 0x1C > > lowercase hex > >> +#define LM_BORDER_COLOR_1_V12 0x20 >> + >> +/* >= v12 DPU with offset to mixer base + stage base */ >> +#define LM_BLEND0_CONST_ALPHA_V12 0x08 > > This doesn't seem to be aligned properly That's only patch view... because I used tabs. I think existing code uses spaces, so I will switch to spaces. Best regards, Krzysztof
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index b9fe3a7343d54f6f8b5aad7982928d5fc728bd61..7a35939ece180c15898b2eaa2f1f451767c741ae 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -319,15 +319,21 @@ static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc, return true; } -static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, - struct dpu_plane_state *pstate, const struct msm_format *format) +static void _dpu_crtc_setup_blend_cfg(const struct dpu_hw_ctl *ctl, + struct dpu_crtc_mixer *mixer, + struct dpu_plane_state *pstate, + const struct msm_format *format) { struct dpu_hw_mixer *lm = mixer->hw_lm; uint32_t blend_op; - uint32_t fg_alpha, bg_alpha; + uint32_t fg_alpha, bg_alpha, max_alpha; fg_alpha = pstate->base.alpha >> 8; - bg_alpha = 0xff - fg_alpha; + if (ctl->mdss_ver->core_major_ver < 12) + max_alpha = 0xff; + else + max_alpha = 0x3ff; + bg_alpha = max_alpha - fg_alpha; /* default to opaque blending */ if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE || @@ -337,7 +343,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, } else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { blend_op = DPU_BLEND_FG_ALPHA_FG_CONST | DPU_BLEND_BG_ALPHA_FG_PIXEL; - if (fg_alpha != 0xff) { + if (fg_alpha != max_alpha) { bg_alpha = fg_alpha; blend_op |= DPU_BLEND_BG_MOD_ALPHA | DPU_BLEND_BG_INV_MOD_ALPHA; @@ -348,7 +354,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, /* coverage blending */ blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL | DPU_BLEND_BG_ALPHA_FG_PIXEL; - if (fg_alpha != 0xff) { + if (fg_alpha != max_alpha) { bg_alpha = fg_alpha; blend_op |= DPU_BLEND_FG_MOD_ALPHA | DPU_BLEND_FG_INV_MOD_ALPHA | @@ -482,7 +488,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, /* blend config update */ for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) { - _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format); + _dpu_crtc_setup_blend_cfg(ctl, mixer + lm_idx, pstate, format); if (bg_alpha_enable && !format->alpha_enable) mixer[lm_idx].mixer_op_mode = 0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 3bfb61cb83672dca4236bdbbbfb1e442223576d2..75bf3521b03c8e243ccfe1fc226aa71f23b296df 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -19,12 +19,20 @@ /* These register are offset to mixer base + stage base */ #define LM_BLEND0_OP 0x00 + +/* <v12 DPU with offset to mixer base + stage base */ #define LM_BLEND0_CONST_ALPHA 0x04 #define LM_FG_COLOR_FILL_COLOR_0 0x08 #define LM_FG_COLOR_FILL_COLOR_1 0x0C #define LM_FG_COLOR_FILL_SIZE 0x10 #define LM_FG_COLOR_FILL_XY 0x14 +/* >= v12 DPU */ +#define LM_BORDER_COLOR_0_V12 0x1C +#define LM_BORDER_COLOR_1_V12 0x20 + +/* >= v12 DPU with offset to mixer base + stage base */ +#define LM_BLEND0_CONST_ALPHA_V12 0x08 #define LM_BLEND0_FG_ALPHA 0x04 #define LM_BLEND0_BG_ALPHA 0x08 @@ -83,6 +91,22 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, } } +static void dpu_hw_lm_setup_border_color_v12(struct dpu_hw_mixer *ctx, + struct dpu_mdss_color *color, + u8 border_en) +{ + struct dpu_hw_blk_reg_map *c = &ctx->hw; + + if (border_en) { + DPU_REG_WRITE(c, LM_BORDER_COLOR_0_V12, + (color->color_0 & 0x3ff) | + ((color->color_1 & 0x3ff) << 16)); + DPU_REG_WRITE(c, LM_BORDER_COLOR_1_V12, + (color->color_2 & 0x3ff) | + ((color->color_3 & 0x3ff) << 16)); + } +} + static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx) { dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0); @@ -112,6 +136,27 @@ static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); } +static void +dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx, + u32 stage, u32 fg_alpha, + u32 bg_alpha, u32 blend_op) +{ + struct dpu_hw_blk_reg_map *c = &ctx->hw; + int stage_off; + u32 const_alpha; + + if (stage == DPU_STAGE_BASE) + return; + + stage_off = _stage_offset(ctx, stage); + if (WARN_ON(stage_off < 0)) + return; + + const_alpha = (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16); + DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha); + DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); +} + static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) { @@ -144,6 +189,32 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx, DPU_REG_WRITE(c, LM_OP_MODE, op_mode); } +static void dpu_hw_lm_setup_color3_v12(struct dpu_hw_mixer *ctx, + uint32_t mixer_op_mode) +{ + struct dpu_hw_blk_reg_map *c = &ctx->hw; + int op_mode, stages, stage_off, i; + + stages = ctx->cap->sblk->maxblendstages; + if (stages <= 0) + return; + + for (i = DPU_STAGE_0; i <= stages; i++) { + stage_off = _stage_offset(ctx, i); + if (WARN_ON(stage_off < 0)) + return; + + /* set color_out3 bit in blend0_op when enabled in mixer_op_mode */ + op_mode = DPU_REG_READ(c, LM_BLEND0_OP + stage_off); + if (mixer_op_mode & BIT(i)) + op_mode |= BIT(30); + else + op_mode &= ~BIT(30); + + DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, op_mode); + } +} + /** * dpu_hw_lm_init() - Initializes the mixer hw driver object. * should be called once before accessing every mixer. @@ -175,12 +246,19 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev, c->idx = cfg->id; c->cap = cfg; c->ops.setup_mixer_out = dpu_hw_lm_setup_out; - if (mdss_ver->core_major_ver >= 4) + if (mdss_ver->core_major_ver >= 12) + c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha_v12; + else if (mdss_ver->core_major_ver >= 4) c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha; else c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config; - c->ops.setup_alpha_out = dpu_hw_lm_setup_color3; - c->ops.setup_border_color = dpu_hw_lm_setup_border_color; + if (mdss_ver->core_major_ver < 12) { + c->ops.setup_alpha_out = dpu_hw_lm_setup_color3; + c->ops.setup_border_color = dpu_hw_lm_setup_border_color; + } else { + c->ops.setup_alpha_out = dpu_hw_lm_setup_color3_v12; + c->ops.setup_border_color = dpu_hw_lm_setup_border_color_v12; + } c->ops.setup_misr = dpu_hw_lm_setup_misr; c->ops.collect_misr = dpu_hw_lm_collect_misr;
v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register differences and new implementations of setup_alpha_out, setup_border_color and so one for this. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 20 +++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 84 +++++++++++++++++++++++++++++-- 2 files changed, 94 insertions(+), 10 deletions(-)