@@ -25,6 +25,28 @@
#include <asm/io.h>
#include <asm/arch/system.h>
+static void exynos5_set_usbhost_mode(unsigned int mode)
+{
+ struct exynos5_sysreg *sysreg =
+ (struct exynos5_sysreg *)samsung_get_base_sysreg();
+ unsigned int phy_cfg;
+
+ /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
+ if (mode == USB20_PHY_CFG_HOST_LINK_EN) {
+ setbits_le32(&sysreg->usb20phy_cfg,
+ USB20_PHY_CFG_HOST_LINK_EN);
+ } else {
+ clrbits_le32(&sysreg->usb20phy_cfg,
+ USB20_PHY_CFG_HOST_LINK_EN);
+ }
+}
+
+void set_usbhost_mode(unsigned int mode)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_usbhost_mode(mode);
+}
+
static void exynos4_set_system_display(void)
{
struct exynos4_sysreg *sysreg =
@@ -49,6 +49,9 @@ struct exynos5_sysreg {
};
#endif
+#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0)
+
+void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
#endif /* _EXYNOS4_SYSTEM_H */
@@ -24,12 +24,15 @@
#include <usb.h>
#include <asm/arch/cpu.h>
#include <asm/arch/ehci.h>
+#include <asm/arch/system.h>
#include "ehci.h"
#include "ehci-core.h"
/* Setup the EHCI host controller. */
static void setup_usb_phy(struct exynos_usb_phy *usb)
{
+ set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
+
clrbits_le32(&usb->usbphyctrl0,
HOST_CTRL0_FSEL_MASK |
HOST_CTRL0_COMMONON_N |
This patch adds a function to set usb host mode to USB 2.0 HOST Link for EXYNOS5 Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> --- arch/arm/cpu/armv7/exynos/system.c | 22 ++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/system.h | 3 +++ drivers/usb/host/ehci-exynos.c | 3 +++ 3 files changed, 28 insertions(+), 0 deletions(-)