Message ID | 20250120130936.1080069-4-claudiu.beznea.uj@bp.renesas.com |
---|---|
State | New |
Headers | show |
Series | Add support for the rest of Renesas RZ/G3S serial interfaces | expand |
On Mon, Jan 20, 2025 at 2:09 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Enable SCIF3. It is routed on the RZ SMARC Carrier II board on SER1_UART > interface. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > > Changes in v4: > - dropped checking the SW_CONFIG3 > - dropped the include of rzg3s-smarc-switches.h Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.15. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 81b4ffd1417d..0851e0b7ed40 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -12,6 +12,7 @@ / { aliases { i2c0 = &i2c0; + serial1 = &scif3; serial3 = &scif0; mmc1 = &sdhi1; }; @@ -162,6 +163,11 @@ scif0_pins: scif0 { <RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */ }; + scif3_pins: scif3 { + pinmux = <RZG2L_PORT_PINMUX(17, 2, 7)>, /* RXD */ + <RZG2L_PORT_PINMUX(17, 3, 7)>; /* TXD */ + }; + sdhi1_pins: sd1 { data { pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; @@ -208,6 +214,12 @@ &scif0 { status = "okay"; }; +&scif3 { + pinctrl-names = "default"; + pinctrl-0 = <&scif3_pins>; + status = "okay"; +}; + &sdhi1 { pinctrl-0 = <&sdhi1_pins>; pinctrl-1 = <&sdhi1_pins_uhs>;