@@ -91,10 +91,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
return;
}
- /* Init internal devices */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
-
if (cpu_mips_itu_supported(env)) {
itu_present = true;
/* Attach ITC Tag to the VP */
@@ -277,10 +277,6 @@ static void mips_fuloong2e_init(MachineState *machine)
}
}
- /* Init internal devices */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
-
/* North bridge, Bonito --> IP2 */
pci_bus = bonito_init(env->irq[2]);
@@ -259,10 +259,6 @@ static void mips_jazz_init(MachineState *machine,
exit(1);
}
- /* Init CPU internal devices */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
-
/* Chipset */
rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
sysbus = SYS_BUS_DEVICE(rc4030);
@@ -568,10 +568,6 @@ static void mips_loongson3_virt_init(MachineState *machine)
/* init CPUs */
cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false);
-
- /* Init internal devices */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
qemu_register_reset(main_cpu_reset, cpu);
if (!kvm_enabled()) {
@@ -1037,10 +1037,6 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
for (i = 0; i < ms->smp.cpus; i++) {
cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk,
TARGET_BIG_ENDIAN);
-
- /* Init internal devices */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
qemu_register_reset(main_cpu_reset, cpu);
}
@@ -203,10 +203,6 @@ mips_mipssim_init(MachineState *machine)
reset_info->vector = load_kernel();
}
- /* Init CPU internal devices. */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
-
/*
* Register 64 KB of ISA IO space at 0x1fd00000. But without interrupts
* (except for the hardcoded serial port interrupt) -device cannot work,
@@ -476,6 +476,11 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
fpu_init(env, env->cpu_model);
mvp_init(env);
+ /* Init internal devices */
+#ifndef CONFIG_USER_ONLY
+ cpu_mips_irq_init_cpu(cpu);
+ cpu_mips_clock_init(cpu);
+#endif
if (!clock_get(cpu->clock)) {
#ifndef CONFIG_USER_ONLY
if (!qtest_enabled()) {
The MIPS timer and IRQs are tied to the CPU. Creating them outside in board code isn't correct. Do it once in the DeviceRealize() handler. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/mips/cps.c | 4 ---- hw/mips/fuloong2e.c | 4 ---- hw/mips/jazz.c | 4 ---- hw/mips/loongson3_virt.c | 4 ---- hw/mips/malta.c | 4 ---- hw/mips/mipssim.c | 4 ---- target/mips/cpu.c | 5 +++++ 7 files changed, 5 insertions(+), 24 deletions(-)