| Message ID | 20250117-sa8775p-lmh-interrupts-v1-1-bae549f0bfe8@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: qcom: sa8775p: Add LMH interrupts for cpufreq_hw node | expand |
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 3394ae2d13003417a15e64c9e47833725ec779e6..1408b946dfd589aef49f25d805c5fa63d1e64543 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -4660,6 +4660,10 @@ cpufreq_hw: cpufreq@18591000 { <0x0 0x18593000 0x0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate";
Add LMH interrupts for cpufreq_hw node to indicate if there is any thermal throttle. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> --- This patch was previously included in the below SA8775P DDR & L3 scaling series: https://lore.kernel.org/all/20241112-sa8775p-cpufreq-l3-ddr-scaling-v2-0-53d256b3f2a7@quicinc.com/ Based on Bjorn's review comments on the above series, included DDR & L3 scaling patch in it's dependent interconnect series and posting the LMH interrupts patch separately here. --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++++ 1 file changed, 4 insertions(+) --- base-commit: 0907e7fb35756464aa34c35d6abb02998418164b change-id: 20250117-sa8775p-lmh-interrupts-5f8a61968372 Best regards,