| Message ID | 20250117182456.2077110-1-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show
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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 00/68] tcg patch queue
Date: Fri, 17 Jan 2025 10:23:48 -0800
Message-ID: <20250117182456.2077110-1-richard.henderson@linaro.org>
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|
Note that I have refreshed the expiry of my public key. and pushed to keys.openpgp.org. r~ The following changes since commit 4d5d933bbc7cc52f6cc6b9021f91fa06266222d5: Merge tag 'pull-xenfv-20250116' of git://git.infradead.org/users/dwmw2/qemu into staging (2025-01-16 09:03:43 -0500) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250117 for you to fetch changes up to db1649823d4f27b924a5aa5f9e0111457accb798: softfloat: Constify helpers returning float_status field (2025-01-17 08:29:25 -0800) ---------------------------------------------------------------- tcg: - Add TCGOP_TYPE, TCGOP_FLAGS. - Pass type and flags to tcg_op_supported, tcg_target_op_def. - Split out tcg-target-has.h and unexport from tcg.h. - Reorg constraint processing; constify TCGOpDef. - Make extract, sextract, deposit opcodes mandatory. - Merge ext{8,16,32}{s,u} opcodes into {s}extract. tcg/mips: Expand bswap unconditionally tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 tcg/riscv: Use BEXTI for single-bit extractions tcg/sparc64: Use SRA, SRL for {s}extract_i64 disas/riscv: Guard dec->cfg dereference for host disassemble util/cpuinfo-riscv: Detect Zbs accel/tcg: Call tcg_tb_insert() for one-insn TBs linux-user: Add missing /proc/cpuinfo fields for sparc ---------------------------------------------------------------- Helge Deller (1): linux-user: Add missing /proc/cpuinfo fields for sparc Ilya Leoshkevich (2): tcg: Document tb_lookup() and tcg_tb_lookup() accel/tcg: Call tcg_tb_insert() for one-insn TBs LIU Zhiwei (1): disas/riscv: Guard dec->cfg dereference for host disassemble Philippe Mathieu-Daudé (1): softfloat: Constify helpers returning float_status field Richard Henderson (63): tcg: Move call abi parameters from tcg-target.h to tcg-target.c.inc tcg: Replace TCGOP_VECL with TCGOP_TYPE tcg: Move tcg_op_insert_{after,before} decls to tcg-internal.h tcg: Copy TCGOP_TYPE in tcg_op_insert_{after,before} tcg: Add TCGOP_FLAGS tcg: Add type and flags arguments to tcg_op_supported target/arm: Do not test TCG_TARGET_HAS_bitsel_vec target/arm: Use tcg_op_supported target/tricore: Use tcg_op_supported tcg: Add tcg_op_deposit_valid target/i386: Remove TCG_TARGET_extract_tl_valid target/i386: Use tcg_op_deposit_valid target/i386: Use tcg_op_supported tcg: Remove TCG_TARGET_NEED_LDST_LABELS and TCG_TARGET_NEED_POOL_LABELS tcg: Rename tcg-target.opc.h to tcg-target-opc.h.inc tcg/tci: Move TCI specific opcodes to tcg-target-opc.h.inc tcg: Move fallback tcg_can_emit_vec_op out of line tcg/ppc: Remove TCGPowerISA enum tcg: Extract default TCG_TARGET_HAS_foo definitions to 'tcg-has.h' tcg/aarch64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' tcg/arm: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' tcg/i386: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' tcg/loongarch64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' tcg/mips: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' tcg/ppc: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' tcg/riscv: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' tcg/s390x: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' tcg/sparc64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' tcg/tci: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' tcg: Include 'tcg-target-has.h' once in 'tcg-has.h' tcg: Only include 'tcg-has.h' when necessary tcg: Split out tcg-target-mo.h tcg: Use C_NotImplemented in tcg_target_op_def tcg: Change have_vec to has_type in tcg_op_supported tcg: Reorg process_op_defs tcg: Remove args_ct from TCGOpDef tcg: Constify tcg_op_defs tcg: Validate op supported in opcode_args_ct tcg: Add TCG_OPF_NOT_PRESENT to opcodes without inputs or outputs tcg: Pass type and flags to tcg_target_op_def tcg: Add TCGType argument to tcg_out_op tcg: Remove TCG_OPF_64BIT tcg: Drop implementation checks from tcg-opc.h tcg: Replace IMPLVEC with TCG_OPF_VECTOR tcg/mips: Expand bswap unconditionally tcg/i386: Handle all 8-bit extensions for i686 tcg/i386: Fold the ext{8,16,32}[us] cases into {s}extract tcg/aarch64: Provide TCG_TARGET_{s}extract_valid tcg/aarch64: Expand extract with offset 0 with andi tcg/arm: Add full [US]XT[BH] into {s}extract tcg/loongarch64: Fold the ext{8,16,32}[us] cases into {s}extract tcg/mips: Fold the ext{8,16,32}[us] cases into {s}extract tcg/ppc: Fold the ext{8,16,32}[us] cases into {s}extract tcg/riscv64: Fold the ext{8,16,32}[us] cases into {s}extract tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 tcg/s390x: Fold the ext{8,16,32}[us] cases into {s}extract tcg/sparc64: Use SRA, SRL for {s}extract_i64 tcg/tci: Provide TCG_TARGET_{s}extract_valid tcg/tci: Remove assertions for deposit and extract tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64} tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64} util/cpuinfo-riscv: Detect Zbs tcg/riscv: Use BEXTI for single-bit extractions accel/tcg/internal-target.h | 1 + host/include/riscv/host/cpuinfo.h | 5 +- include/fpu/softfloat-helpers.h | 25 +- include/tcg/tcg-opc.h | 355 +++++------- include/tcg/tcg.h | 187 ++---- linux-user/sparc/target_proc.h | 20 +- tcg/aarch64/tcg-target-has.h | 117 ++++ tcg/aarch64/tcg-target-mo.h | 12 + tcg/aarch64/tcg-target.h | 126 ---- tcg/arm/tcg-target-has.h | 100 ++++ tcg/arm/tcg-target-mo.h | 13 + tcg/arm/tcg-target.h | 86 --- tcg/i386/tcg-target-has.h | 169 ++++++ tcg/i386/tcg-target-mo.h | 19 + tcg/i386/tcg-target.h | 162 ------ tcg/loongarch64/tcg-target-has.h | 119 ++++ tcg/loongarch64/tcg-target-mo.h | 12 + tcg/loongarch64/tcg-target.h | 115 ---- tcg/mips/tcg-target-has.h | 135 +++++ tcg/mips/tcg-target-mo.h | 13 + tcg/mips/tcg-target.h | 130 ----- tcg/ppc/tcg-target-has.h | 131 +++++ tcg/ppc/tcg-target-mo.h | 12 + tcg/ppc/tcg-target.h | 126 ---- tcg/riscv/tcg-target-has.h | 135 +++++ tcg/riscv/tcg-target-mo.h | 12 + tcg/riscv/tcg-target.h | 116 ---- tcg/s390x/tcg-target-has.h | 137 +++++ tcg/s390x/tcg-target-mo.h | 12 + tcg/s390x/tcg-target.h | 126 ---- tcg/sparc64/tcg-target-has.h | 87 +++ tcg/sparc64/tcg-target-mo.h | 12 + tcg/sparc64/tcg-target.h | 91 --- tcg/tcg-has.h | 101 ++++ tcg/tcg-internal.h | 18 +- tcg/tci/tcg-target-has.h | 81 +++ tcg/tci/tcg-target-mo.h | 17 + tcg/tci/tcg-target.h | 94 --- accel/tcg/cpu-exec.c | 15 +- accel/tcg/translate-all.c | 29 +- disas/riscv.c | 23 +- target/arm/tcg/translate-a64.c | 10 +- target/arm/tcg/translate-sve.c | 22 +- target/arm/tcg/translate.c | 2 +- target/tricore/translate.c | 4 +- tcg/optimize.c | 27 +- tcg/tcg-common.c | 5 +- tcg/tcg-op-gvec.c | 1 + tcg/tcg-op-ldst.c | 29 +- tcg/tcg-op-vec.c | 9 +- tcg/tcg-op.c | 149 ++--- tcg/tcg.c | 643 ++++++++++++++------- tcg/tci.c | 13 +- util/cpuinfo-riscv.c | 18 +- docs/devel/tcg-ops.rst | 15 +- target/i386/tcg/emit.c.inc | 14 +- .../{tcg-target.opc.h => tcg-target-opc.h.inc} | 4 +- tcg/aarch64/tcg-target.c.inc | 33 +- tcg/arm/{tcg-target.opc.h => tcg-target-opc.h.inc} | 6 +- tcg/arm/tcg-target.c.inc | 71 ++- .../{tcg-target.opc.h => tcg-target-opc.h.inc} | 22 +- tcg/i386/tcg-target.c.inc | 121 +++- .../{tcg-target.opc.h => tcg-target-opc.h.inc} | 0 tcg/loongarch64/tcg-target.c.inc | 59 +- tcg/mips/tcg-target-opc.h.inc | 1 + tcg/mips/tcg-target.c.inc | 55 +- tcg/ppc/{tcg-target.opc.h => tcg-target-opc.h.inc} | 12 +- tcg/ppc/tcg-target.c.inc | 39 +- .../{tcg-target.opc.h => tcg-target-opc.h.inc} | 0 tcg/riscv/tcg-target.c.inc | 66 ++- .../{tcg-target.opc.h => tcg-target-opc.h.inc} | 6 +- tcg/s390x/tcg-target.c.inc | 59 +- tcg/sparc64/tcg-target-opc.h.inc | 1 + tcg/sparc64/tcg-target.c.inc | 29 +- tcg/tcg-ldst.c.inc | 65 --- tcg/tcg-pool.c.inc | 162 ------ tcg/tci/tcg-target-opc.h.inc | 4 + tcg/tci/tcg-target.c.inc | 53 +- 78 files changed, 2856 insertions(+), 2269 deletions(-) create mode 100644 tcg/aarch64/tcg-target-has.h create mode 100644 tcg/aarch64/tcg-target-mo.h create mode 100644 tcg/arm/tcg-target-has.h create mode 100644 tcg/arm/tcg-target-mo.h create mode 100644 tcg/i386/tcg-target-has.h create mode 100644 tcg/i386/tcg-target-mo.h create mode 100644 tcg/loongarch64/tcg-target-has.h create mode 100644 tcg/loongarch64/tcg-target-mo.h create mode 100644 tcg/mips/tcg-target-has.h create mode 100644 tcg/mips/tcg-target-mo.h create mode 100644 tcg/ppc/tcg-target-has.h create mode 100644 tcg/ppc/tcg-target-mo.h create mode 100644 tcg/riscv/tcg-target-has.h create mode 100644 tcg/riscv/tcg-target-mo.h create mode 100644 tcg/s390x/tcg-target-has.h create mode 100644 tcg/s390x/tcg-target-mo.h create mode 100644 tcg/sparc64/tcg-target-has.h create mode 100644 tcg/sparc64/tcg-target-mo.h create mode 100644 tcg/tcg-has.h create mode 100644 tcg/tci/tcg-target-has.h create mode 100644 tcg/tci/tcg-target-mo.h rename tcg/aarch64/{tcg-target.opc.h => tcg-target-opc.h.inc} (82%) rename tcg/arm/{tcg-target.opc.h => tcg-target-opc.h.inc} (75%) rename tcg/i386/{tcg-target.opc.h => tcg-target-opc.h.inc} (72%) rename tcg/loongarch64/{tcg-target.opc.h => tcg-target-opc.h.inc} (100%) create mode 100644 tcg/mips/tcg-target-opc.h.inc rename tcg/ppc/{tcg-target.opc.h => tcg-target-opc.h.inc} (83%) rename tcg/riscv/{tcg-target.opc.h => tcg-target-opc.h.inc} (100%) rename tcg/s390x/{tcg-target.opc.h => tcg-target-opc.h.inc} (75%) create mode 100644 tcg/sparc64/tcg-target-opc.h.inc delete mode 100644 tcg/tcg-ldst.c.inc delete mode 100644 tcg/tcg-pool.c.inc create mode 100644 tcg/tci/tcg-target-opc.h.inc