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[PULL,06/68] tcg: Add TCGOP_FLAGS

Message ID	20250117182456.2077110-7-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 06/68] tcg: Add TCGOP_FLAGS Date: Fri, 17 Jan 2025 10:23:54 -0800 Message-ID: <20250117182456.2077110-7-richard.henderson@linaro.org> In-Reply-To: <20250117182456.2077110-1-richard.henderson@linaro.org> References: <20250117182456.2077110-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/68] disas/riscv: Guard dec->cfg dereference for host disassemble \| expand [PULL,01/68] disas/riscv: Guard dec->cfg dereference for host disassemble [PULL,02/68] tcg: Move call abi parameters from tcg-target.h to tcg-target.c.inc [PULL,03/68] tcg: Replace TCGOP_VECL with TCGOP_TYPE [PULL,04/68] tcg: Move tcg_op_insert_{after, before} decls to tcg-internal.h [PULL,05/68] tcg: Copy TCGOP_TYPE in tcg_op_insert_{after,before} [PULL,06/68] tcg: Add TCGOP_FLAGS [PULL,07/68] tcg: Add type and flags arguments to tcg_op_supported [PULL,08/68] target/arm: Do not test TCG_TARGET_HAS_bitsel_vec [PULL,09/68] target/arm: Use tcg_op_supported [PULL,10/68] target/tricore: Use tcg_op_supported [PULL,11/68] tcg: Add tcg_op_deposit_valid [PULL,12/68] target/i386: Remove TCG_TARGET_extract_tl_valid [PULL,13/68] target/i386: Use tcg_op_deposit_valid [PULL,14/68] target/i386: Use tcg_op_supported [PULL,15/68] tcg: Remove TCG_TARGET_NEED_LDST_LABELS and TCG_TARGET_NEED_POOL_LABELS [PULL,16/68] tcg: Rename tcg-target.opc.h to tcg-target-opc.h.inc [PULL,17/68] tcg/tci: Move TCI specific opcodes to tcg-target-opc.h.inc [PULL,18/68] tcg: Move fallback tcg_can_emit_vec_op out of line [PULL,19/68] tcg/ppc: Remove TCGPowerISA enum [PULL,20/68] tcg: Extract default TCG_TARGET_HAS_foo definitions to 'tcg-has.h' [PULL,21/68] tcg/aarch64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' [PULL,22/68] tcg/arm: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' [PULL,23/68] tcg/i386: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' [PULL,24/68] tcg/loongarch64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' [PULL,25/68] tcg/mips: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' [PULL,26/68] tcg/ppc: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' [PULL,27/68] tcg/riscv: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' [PULL,28/68] tcg/s390x: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' [PULL,29/68] tcg/sparc64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' [PULL,30/68] tcg/tci: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h' [PULL,31/68] tcg: Include 'tcg-target-has.h' once in 'tcg-has.h' [PULL,32/68] tcg: Only include 'tcg-has.h' when necessary [PULL,33/68] tcg: Split out tcg-target-mo.h [PULL,34/68] tcg: Use C_NotImplemented in tcg_target_op_def [PULL,35/68] tcg: Change have_vec to has_type in tcg_op_supported [PULL,36/68] tcg: Reorg process_op_defs [PULL,37/68] tcg: Remove args_ct from TCGOpDef [PULL,38/68] tcg: Constify tcg_op_defs [PULL,39/68] tcg: Validate op supported in opcode_args_ct [PULL,40/68] tcg: Add TCG_OPF_NOT_PRESENT to opcodes without inputs or outputs [PULL,41/68] tcg: Pass type and flags to tcg_target_op_def [PULL,42/68] tcg: Add TCGType argument to tcg_out_op [PULL,43/68] tcg: Remove TCG_OPF_64BIT [PULL,44/68] tcg: Drop implementation checks from tcg-opc.h [PULL,45/68] tcg: Replace IMPLVEC with TCG_OPF_VECTOR [PULL,46/68] tcg/mips: Expand bswap unconditionally [PULL,47/68] tcg/i386: Handle all 8-bit extensions for i686 [PULL,48/68] tcg/i386: Fold the ext{8, 16, 32}[us] cases into {s}extract [PULL,49/68] tcg/aarch64: Provide TCG_TARGET_{s}extract_valid [PULL,50/68] tcg/aarch64: Expand extract with offset 0 with andi [PULL,51/68] tcg/arm: Add full [US]XT[BH] into {s}extract [PULL,52/68] tcg/loongarch64: Fold the ext{8, 16, 32}[us] cases into {s}extract [PULL,53/68] tcg/mips: Fold the ext{8, 16, 32}[us] cases into {s}extract [PULL,54/68] tcg/ppc: Fold the ext{8, 16, 32}[us] cases into {s}extract [PULL,55/68] tcg/riscv64: Fold the ext{8, 16, 32}[us] cases into {s}extract [PULL,56/68] tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 [PULL,57/68] tcg/s390x: Fold the ext{8, 16, 32}[us] cases into {s}extract [PULL,58/68] tcg/sparc64: Use SRA, SRL for {s}extract_i64 [PULL,59/68] tcg/tci: Provide TCG_TARGET_{s}extract_valid [PULL,60/68] tcg/tci: Remove assertions for deposit and extract [PULL,61/68] tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64} [PULL,62/68] tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64} [PULL,63/68] util/cpuinfo-riscv: Detect Zbs [PULL,64/68] tcg/riscv: Use BEXTI for single-bit extractions [PULL,65/68] linux-user: Add missing /proc/cpuinfo fields for sparc [PULL,66/68] tcg: Document tb_lookup() and tcg_tb_lookup() [PULL,67/68] accel/tcg: Call tcg_tb_insert() for one-insn TBs [PULL,68/68] softfloat: Constify helpers returning float_status field

Commit Message

Richard Henderson Jan. 17, 2025, 6:23 p.m. UTC

To be used by some integer operations instead of,
or in addition to, a trailing constant argument.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg.h | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 5d96cdfc30..238c55c9ac 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -440,6 +440,7 @@  struct TCGOp {
 #define TCGOP_CALLO(X)    (X)->param2
 
 #define TCGOP_TYPE(X)     (X)->param1
+#define TCGOP_FLAGS(X)    (X)->param2
 #define TCGOP_VECE(X)     (X)->param2
 
 /* Make sure operands fit in the bitfields above.  */