| Message ID | 20250112225614.33723-3-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | hw/arm/v7m: Remove Cortex-M &first_cpu uses | expand |
On 12/1/25 23:56, Philippe Mathieu-Daudé wrote: > While the TYPE_ARMV7M object forward its NVIC interrupt lines, > it is somehow misleading to name it 'nvic'. Add the 'armv7m' > local variable for clarity, but also keep the 'nvic' variable > behaving like before when used for wiring IRQ lines. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > hw/arm/stellaris.c | 21 +++++++++++---------- > 1 file changed, 11 insertions(+), 10 deletions(-) Note this patch diverges with my other Stellaris series: https://lore.kernel.org/qemu-devel/20250110160204.74997-1-philmd@linaro.org/ I'm OK to rebase whichever isn't merged first (this one being less work).
On Mon, Jan 13, 2025 at 8:57 AM Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > > While the TYPE_ARMV7M object forward its NVIC interrupt lines, > it is somehow misleading to name it 'nvic'. Add the 'armv7m' > local variable for clarity, but also keep the 'nvic' variable > behaving like before when used for wiring IRQ lines. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/arm/stellaris.c | 21 +++++++++++---------- > 1 file changed, 11 insertions(+), 10 deletions(-) > > diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c > index 1bba96df14e..7303e096ef7 100644 > --- a/hw/arm/stellaris.c > +++ b/hw/arm/stellaris.c > @@ -1031,7 +1031,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) > */ > > Object *soc_container; > - DeviceState *gpio_dev[7], *nvic; > + DeviceState *gpio_dev[7], *armv7m, *nvic; > qemu_irq gpio_in[7][8]; > qemu_irq gpio_out[7][8]; > qemu_irq adc; > @@ -1095,19 +1095,20 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) > qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); > sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); > > - nvic = qdev_new(TYPE_ARMV7M); > - object_property_add_child(soc_container, "v7m", OBJECT(nvic)); > - qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); > - qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS); > - qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); > - qdev_prop_set_bit(nvic, "enable-bitband", true); > - qdev_connect_clock_in(nvic, "cpuclk", > + armv7m = qdev_new(TYPE_ARMV7M); > + object_property_add_child(soc_container, "v7m", OBJECT(armv7m)); > + qdev_prop_set_uint32(armv7m, "num-irq", NUM_IRQ_LINES); > + qdev_prop_set_uint8(armv7m, "num-prio-bits", NUM_PRIO_BITS); > + qdev_prop_set_string(armv7m, "cpu-type", ms->cpu_type); > + qdev_prop_set_bit(armv7m, "enable-bitband", true); > + qdev_connect_clock_in(armv7m, "cpuclk", > qdev_get_clock_out(ssys_dev, "SYSCLK")); > /* This SoC does not connect the systick reference clock */ > - object_property_set_link(OBJECT(nvic), "memory", > + object_property_set_link(OBJECT(armv7m), "memory", > OBJECT(get_system_memory()), &error_abort); > /* This will exit with an error if the user passed us a bad cpu_type */ > - sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); > + sysbus_realize_and_unref(SYS_BUS_DEVICE(armv7m), &error_fatal); > + nvic = armv7m; > > /* Now we can wire up the IRQ and MMIO of the system registers */ > sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); > -- > 2.47.1 > >
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 1bba96df14e..7303e096ef7 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1031,7 +1031,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) */ Object *soc_container; - DeviceState *gpio_dev[7], *nvic; + DeviceState *gpio_dev[7], *armv7m, *nvic; qemu_irq gpio_in[7][8]; qemu_irq gpio_out[7][8]; qemu_irq adc; @@ -1095,19 +1095,20 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4); sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); - nvic = qdev_new(TYPE_ARMV7M); - object_property_add_child(soc_container, "v7m", OBJECT(nvic)); - qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); - qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS); - qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); - qdev_prop_set_bit(nvic, "enable-bitband", true); - qdev_connect_clock_in(nvic, "cpuclk", + armv7m = qdev_new(TYPE_ARMV7M); + object_property_add_child(soc_container, "v7m", OBJECT(armv7m)); + qdev_prop_set_uint32(armv7m, "num-irq", NUM_IRQ_LINES); + qdev_prop_set_uint8(armv7m, "num-prio-bits", NUM_PRIO_BITS); + qdev_prop_set_string(armv7m, "cpu-type", ms->cpu_type); + qdev_prop_set_bit(armv7m, "enable-bitband", true); + qdev_connect_clock_in(armv7m, "cpuclk", qdev_get_clock_out(ssys_dev, "SYSCLK")); /* This SoC does not connect the systick reference clock */ - object_property_set_link(OBJECT(nvic), "memory", + object_property_set_link(OBJECT(armv7m), "memory", OBJECT(get_system_memory()), &error_abort); /* This will exit with an error if the user passed us a bad cpu_type */ - sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(armv7m), &error_fatal); + nvic = armv7m; /* Now we can wire up the IRQ and MMIO of the system registers */ sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000);
While the TYPE_ARMV7M object forward its NVIC interrupt lines, it is somehow misleading to name it 'nvic'. Add the 'armv7m' local variable for clarity, but also keep the 'nvic' variable behaving like before when used for wiring IRQ lines. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/arm/stellaris.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-)