| Message ID | 20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-5-cb66d55d20cc@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon | expand |
Hi Bryan. On 1/2/25 18:32, Bryan O'Donoghue wrote: > Add in 2 CCI busses. One bus has two CCI bus master pinouts: > cci_i2c_scl0 = gpio101 > cci_i2c_sda0 = gpio102 > cci_i2c_scl1 = gpio103 > cci_i2c_sda1 = gpio104 > > A second bus has a single CCI bus master pinout: > cci_i2c_scl2 = gpio105 > cci_i2c_sda2 = gpio106 I notice that the change assigns "aon_cci" function to gpio235 and gpio236 pins, and they do serve as cci1_i2c1 sda/scl pins, thus here is the second CCI bus master. So, I assume the commit message is not correct... > > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 150 +++++++++++++++++++++++++++++++++ > 1 file changed, 150 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 5c7b0c048d41a4ba3d74bbf77216ad09b652ed30..97ebf5596dfc3caa920ef85722ca8afd49cd3c24 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -4648,6 +4648,84 @@ usb_1_ss1_dwc3_ss: endpoint { > }; > }; > > + cci0: cci@ac15000 { > + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci"; > + reg = <0 0x0ac15000 0 0x1000>; > + > + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CCI_0_CLK>; > + clock-names = "camnoc_axi", > + "cpas_ahb", > + "cci"; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; > + > + pinctrl-0 = <&cci0_default>; > + pinctrl-1 = <&cci0_sleep>; > + pinctrl-names = "default", "sleep"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + cci0_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci0_i2c1: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + cci1: cci@ac16000 { > + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci"; > + reg = <0 0x0ac16000 0 0x1000>; > + > + interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CCI_1_CLK>; > + clock-names = "camnoc_axi", > + "cpas_ahb", > + "cci"; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; > + > + pinctrl-0 = <&cci1_default>; > + pinctrl-1 = <&cci1_sleep>; > + pinctrl-names = "default", "sleep"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + cci1_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci1_i2c1: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > camcc: clock-controller@ade0000 { > compatible = "qcom,x1e80100-camcc"; > reg = <0 0x0ade0000 0 0x20000>; > @@ -5271,6 +5349,78 @@ tlmm: pinctrl@f100000 { > gpio-ranges = <&tlmm 0 0 239>; > wakeup-parent = <&pdc>; > > + cci0_default: cci0-default-state { > + cci0_i2c0_default: cci0-i2c0-default-pins { > + /* cci_i2c_sda0, cci_i2c_scl0 */ > + pins = "gpio101", "gpio102"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + cci0_i2c1_default: cci0-i2c1-default-pins { > + /* cci_i2c_sda1, cci_i2c_scl1 */ > + pins = "gpio103", "gpio104"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; > + > + cci0_sleep: cci0-sleep-state { > + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { > + /* cci_i2c_sda0, cci_i2c_scl0 */ > + pins = "gpio101", "gpio102"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { > + /* cci_i2c_sda1, cci_i2c_scl1 */ > + pins = "gpio103", "gpio104"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + }; > + > + cci1_default: cci1-default-state { > + cci1_i2c0_default: cci1-i2c0-default-pins { > + /* cci_i2c_sda2, cci_i2c_scl2 */ > + pins = "gpio105","gpio106"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + cci1_i2c1_default: cci1-i2c1-default-pins { > + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ > + pins = "gpio235","gpio236"; > + function = "aon_cci"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; > + > + cci1_sleep: cci1-sleep-state { > + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { > + /* cci_i2c_sda2, cci_i2c_scl2 */ > + pins = "gpio105","gpio106"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { > + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ > + pins = "gpio235","gpio236"; > + function = "aon_cci"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + }; > + > qup_i2c0_data_clk: qup-i2c0-data-clk-state { > /* SDA, SCL */ > pins = "gpio0", "gpio1"; > -- Best wishes, Vladimir
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 5c7b0c048d41a4ba3d74bbf77216ad09b652ed30..97ebf5596dfc3caa920ef85722ca8afd49cd3c24 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4648,6 +4648,84 @@ usb_1_ss1_dwc3_ss: endpoint { }; }; + cci0: cci@ac15000 { + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac15000 0 0x1000>; + + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci0_default>; + pinctrl-1 = <&cci0_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac16000 { + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac16000 0 0x1000>; + + interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci1_default>; + pinctrl-1 = <&cci1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,x1e80100-camcc"; reg = <0 0x0ade0000 0 0x20000>; @@ -5271,6 +5349,78 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 239>; wakeup-parent = <&pdc>; + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_i2c1_default: cci0-i2c1-default-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_i2c1_default: cci1-i2c1-default-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins = "gpio235","gpio236"; + function = "aon_cci"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins = "gpio235","gpio236"; + function = "aon_cci"; + drive-strength = <2>; + bias-pull-down; + }; + }; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { /* SDA, SCL */ pins = "gpio0", "gpio1";