@@ -72,6 +72,7 @@ DEF(rotr, 1, 2, 0, TCG_OPF_INT)
DEF(extract, 1, 1, 2, TCG_OPF_INT)
DEF(sextract, 1, 1, 2, TCG_OPF_INT)
DEF(deposit, 1, 2, 2, TCG_OPF_INT)
+DEF(extract2, 1, 2, 1, TCG_OPF_INT)
DEF(brcond, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | TCG_OPF_INT)
DEF(setcond, 1, 2, 1, TCG_OPF_INT)
@@ -81,8 +82,6 @@ DEF(movcond, 1, 4, 1, TCG_OPF_INT)
/* load/store */
DEF(ld_i32, 1, 1, 2, 0)
DEF(st_i32, 0, 2, 2, 0)
-/* shifts/rotates */
-DEF(extract2_i32, 1, 2, 1, 0)
DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
DEF(setcond2_i32, 1, 4, 1, 0)
@@ -96,8 +95,6 @@ DEF(ctpop_i32, 1, 1, 0, 0)
/* load/store */
DEF(ld_i64, 1, 1, 2, 0)
DEF(st_i64, 0, 2, 2, 0)
-/* shifts/rotates */
-DEF(extract2_i64, 1, 2, 1, 0)
/* size changing ops */
DEF(ext_i32_i64, 1, 1, 0, 0)
@@ -1831,12 +1831,12 @@ static bool fold_extract2(OptContext *ctx, TCGOp *op)
uint64_t v2 = arg_info(op->args[2])->val;
int shr = op->args[3];
- if (op->opc == INDEX_op_extract2_i64) {
- v1 >>= shr;
- v2 <<= 64 - shr;
- } else {
+ if (op->type == TCG_TYPE_I32) {
v1 = (uint32_t)v1 >> shr;
v2 = (uint64_t)((int32_t)v2 << (32 - shr));
+ } else {
+ v1 >>= shr;
+ v2 <<= 64 - shr;
}
return tcg_opt_gen_movi(ctx, op, op->args[0], v1 | v2);
}
@@ -2766,7 +2766,7 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_extract:
done = fold_extract(&ctx, op);
break;
- CASE_OP_32_64(extract2):
+ case INDEX_op_extract2:
done = fold_extract2(&ctx, op);
break;
case INDEX_op_ext_i32_i64:
@@ -1070,7 +1070,7 @@ void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
} else if (al == ah) {
tcg_gen_rotri_i32(ret, al, ofs);
} else if (TCG_TARGET_HAS_extract2(TCG_TYPE_I32)) {
- tcg_gen_op4i_i32(INDEX_op_extract2_i32, ret, al, ah, ofs);
+ tcg_gen_op4i_i32(INDEX_op_extract2, ret, al, ah, ofs);
} else {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
tcg_gen_shri_i32(t0, al, ofs);
@@ -2802,7 +2802,7 @@ void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
} else if (al == ah) {
tcg_gen_rotri_i64(ret, al, ofs);
} else if (TCG_TARGET_HAS_extract2(TCG_TYPE_I64)) {
- tcg_gen_op4i_i64(INDEX_op_extract2_i64, ret, al, ah, ofs);
+ tcg_gen_op4i_i64(INDEX_op_extract2, ret, al, ah, ofs);
} else {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
tcg_gen_shri_i64(t0, al, ofs);
@@ -2224,6 +2224,8 @@ bool tcg_op_supported(TCGOpcode op, TCGType type)
return has_type && TCG_TARGET_HAS_div2(type);
case INDEX_op_eqv:
return has_type && TCG_TARGET_HAS_eqv(type);
+ case INDEX_op_extract2:
+ return has_type && TCG_TARGET_HAS_extract2(type);
case INDEX_op_muls2:
return has_type && TCG_TARGET_HAS_muls2(type);
case INDEX_op_mulsh:
@@ -2251,8 +2253,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type)
case INDEX_op_sub2:
return has_type && TCG_TARGET_HAS_sub2(type);
- case INDEX_op_extract2_i32:
- return TCG_TARGET_HAS_extract2(TCG_TYPE_I32);
case INDEX_op_bswap16_i32:
case INDEX_op_bswap32_i32:
return TCG_TARGET_HAS_bswap(TCG_TYPE_I32);
@@ -2271,8 +2271,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type)
case INDEX_op_extrh_i64_i32:
return TCG_TARGET_REG_BITS == 64;
- case INDEX_op_extract2_i64:
- return TCG_TARGET_REG_BITS == 64 && TCG_TARGET_HAS_extract2(TCG_TYPE_I64);
case INDEX_op_bswap16_i64:
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
@@ -19,16 +19,6 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
-/*
- * Sometimes, knowing what the backend has can produce better code.
- * The exact opcode to check depends on 32- vs. 64-bit.
- */
-#ifdef TARGET_X86_64
-#define INDEX_op_extract2_tl INDEX_op_extract2_i64
-#else
-#define INDEX_op_extract2_tl INDEX_op_extract2_i32
-#endif
-
#define MMX_OFFSET(reg) \
({ assert((reg) >= 0 && (reg) <= 7); \
offsetof(CPUX86State, fpregs[reg].mmx); })
@@ -2993,7 +2983,7 @@ static void gen_PMOVMSKB(DisasContext *s, X86DecodedInsn *decode)
tcg_gen_ld8u_tl(s->T0, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1)));
while (vec_len > 8) {
vec_len -= 8;
- if (tcg_op_supported(INDEX_op_extract2_tl, TCG_TYPE_TL)) {
+ if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_TL)) {
/*
* Load the next byte of the result into the high byte of T.
* TCG does a similar expansion of deposit to shl+extract2; by
@@ -2426,8 +2426,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
break;
- case INDEX_op_extract2_i64:
- case INDEX_op_extract2_i32:
+ case INDEX_op_extract2:
tcg_out_extr(s, ext, a0, REG0(2), REG0(1), args[3]);
break;
@@ -2998,8 +2997,7 @@ static TCGConstraintSetIndex tcg_target_op_def(const TCGOp *op)
case INDEX_op_deposit:
return C_O1_I2(r, 0, rZ);
- case INDEX_op_extract2_i32:
- case INDEX_op_extract2_i64:
+ case INDEX_op_extract2:
return C_O1_I2(r, rZ, rZ);
case INDEX_op_add2:
@@ -2133,7 +2133,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
case INDEX_op_sextract:
tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]);
break;
- case INDEX_op_extract2_i32:
+ case INDEX_op_extract2:
/* ??? These optimization vs zero should be generic. */
/* ??? But we can't substitute 2 for 1 in the opcode stream yet. */
if (const_args[1]) {
@@ -2229,7 +2229,7 @@ static TCGConstraintSetIndex tcg_target_op_def(const TCGOp *op)
return C_O0_I2(r, rIN);
case INDEX_op_deposit:
return C_O1_I2(r, 0, rZ);
- case INDEX_op_extract2_i32:
+ case INDEX_op_extract2:
return C_O1_I2(r, rZ, rZ);
case INDEX_op_movcond:
return C_O1_I4(r, r, rIN, rIK, 0);
@@ -3093,7 +3093,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
- OP_32_64(extract2):
+ case INDEX_op_extract2:
/* Note that SHRD outputs to the r/m operand. */
tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0);
tcg_out8(s, args[3]);
@@ -3726,8 +3726,7 @@ static TCGConstraintSetIndex tcg_target_op_def(const TCGOp *op)
case INDEX_op_ctpop_i64:
return C_O1_I1(r, r);
- case INDEX_op_extract2_i32:
- case INDEX_op_extract2_i64:
+ case INDEX_op_extract2:
return C_O1_I2(r, 0, r);
case INDEX_op_deposit:
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/tcg/tcg-opc.h | 5 +---- tcg/optimize.c | 10 +++++----- tcg/tcg-op.c | 4 ++-- tcg/tcg.c | 6 ++---- target/i386/tcg/emit.c.inc | 12 +----------- tcg/aarch64/tcg-target.c.inc | 6 ++---- tcg/arm/tcg-target.c.inc | 4 ++-- tcg/i386/tcg-target.c.inc | 5 ++--- 8 files changed, 17 insertions(+), 35 deletions(-)