[v4,2/7] gpio: Add Nuvoton NCT6694 GPIO support

Message ID	20241227095727.2401257-3-a0282524688@gmail.com
State	New
Headers	show Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30F72156887; Fri, 27 Dec 2024 09:57:54 +0000 (UTC) From: Ming Yu <a0282524688@gmail.com> To: tmyu0@nuvoton.com, lee@kernel.org, linus.walleij@linaro.org, brgl@bgdev.pl, andi.shyti@kernel.org, mkl@pengutronix.de, mailhol.vincent@wanadoo.fr, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, wim@linux-watchdog.org, linux@roeck-us.net, jdelvare@suse.com, alexandre.belloni@bootlin.com Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-i2c@vger.kernel.org, linux-can@vger.kernel.org, netdev@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-rtc@vger.kernel.org, Ming Yu <a0282524688@gmail.com> Subject: [PATCH v4 2/7] gpio: Add Nuvoton NCT6694 GPIO support Date: Fri, 27 Dec 2024 17:57:22 +0800 Message-Id: <20241227095727.2401257-3-a0282524688@gmail.com> In-Reply-To: <20241227095727.2401257-1-a0282524688@gmail.com> References: <20241227095727.2401257-1-a0282524688@gmail.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add Nuvoton NCT6694 MFD drivers \| expand [v4,0/7] Add Nuvoton NCT6694 MFD drivers [v4,2/7] gpio: Add Nuvoton NCT6694 GPIO support [v4,4/7] can: Add Nuvoton NCT6694 CAN support [v4,6/7] hwmon: Add Nuvoton NCT6694 HWMON support

diff --git a/MAINTAINERS b/MAINTAINERS index acb270037642..18bf57f47792 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16726,6 +16726,7 @@ NUVOTON NCT6694 MFD DRIVER M: Ming Yu <tmyu0@nuvoton.com> L: linux-kernel@vger.kernel.org S: Supported +F: drivers/gpio/gpio-nct6694.c F: drivers/mfd/nct6694.c F: include/linux/mfd/nct6694.h diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 93ee3aa092f8..808fbfdbff3b 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1461,6 +1461,18 @@ config GPIO_MAX77650 GPIO driver for MAX77650/77651 PMIC from Maxim Semiconductor. These chips have a single pin that can be configured as GPIO. +config GPIO_NCT6694 + tristate "Nuvoton NCT6694 GPIO controller support" + depends on MFD_NCT6694 + select GENERIC_IRQ_CHIP + select GPIOLIB_IRQCHIP + help + This driver supports 8 GPIO pins per bank that can all be interrupt + sources. + + This driver can also be built as a module. If so, the module will be + called gpio-nct6694. + config GPIO_PALMAS bool "TI PALMAS series PMICs GPIO" depends on MFD_PALMAS diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index af3ba4d81b58..ad80a078b27b 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -123,6 +123,7 @@ obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o obj-$(CONFIG_GPIO_NOMADIK) += gpio-nomadik.o obj-$(CONFIG_GPIO_NPCM_SGPIO) += gpio-npcm-sgpio.o +obj-$(CONFIG_GPIO_NCT6694) += gpio-nct6694.o obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o obj-$(CONFIG_GPIO_OMAP) += gpio-omap.o obj-$(CONFIG_GPIO_PALMAS) += gpio-palmas.o diff --git a/drivers/gpio/gpio-nct6694.c b/drivers/gpio/gpio-nct6694.c new file mode 100644 index 000000000000..14c8acfcf5c3 --- /dev/null +++ b/drivers/gpio/gpio-nct6694.c @@ -0,0 +1,462 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Nuvoton NCT6694 GPIO controller driver based on USB interface. + * + * Copyright (C) 2024 Nuvoton Technology Corp. + */ + +#include <linux/bits.h> +#include <linux/gpio/driver.h> +#include <linux/interrupt.h> +#include <linux/mfd/core.h> +#include <linux/mfd/nct6694.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +/* + * USB command module type for NCT6694 GPIO controller. + * This defines the module type used for communication with the NCT6694 + * GPIO controller over the USB interface. + */ +#define NCT6694_GPIO_MOD 0xFF + +#define NCT6694_GPIO_VER 0x90 +#define NCT6694_GPIO_VALID 0x110 +#define NCT6694_GPI_DATA 0x120 +#define NCT6694_GPO_DIR 0x170 +#define NCT6694_GPO_TYPE 0x180 +#define NCT6694_GPO_DATA 0x190 + +#define NCT6694_GPI_STS 0x130 +#define NCT6694_GPI_CLR 0x140 +#define NCT6694_GPI_FALLING 0x150 +#define NCT6694_GPI_RISING 0x160 + +#define NCT6694_NR_GPIO 8 + +struct nct6694_gpio_data { + struct nct6694 *nct6694; + struct gpio_chip gpio; + struct mutex lock; + /* Protect irq operation */ + struct mutex irq_lock; + + unsigned char reg_val; + unsigned char irq_trig_falling; + unsigned char irq_trig_rising; + + /* Current gpio group */ + unsigned char group; +}; + +static int nct6694_get_direction(struct gpio_chip *gpio, unsigned int offset) +{ + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); + int ret; + + guard(mutex)(&data->lock); + + ret = nct6694_read_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPO_DIR + data->group, + sizeof(data->reg_val), + &data->reg_val); + if (ret < 0) + return ret; + + return !(BIT(offset) & data->reg_val); +} + +static int nct6694_direction_input(struct gpio_chip *gpio, unsigned int offset) +{ + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); + int ret; + + guard(mutex)(&data->lock); + + ret = nct6694_read_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPO_DIR + data->group, + sizeof(data->reg_val), + &data->reg_val); + if (ret < 0) + return ret; + + data->reg_val &= ~BIT(offset); + + return nct6694_write_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPO_DIR + data->group, + sizeof(data->reg_val), + &data->reg_val); +} + +static int nct6694_direction_output(struct gpio_chip *gpio, + unsigned int offset, int val) +{ + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); + int ret; + + guard(mutex)(&data->lock); + + /* Set direction to output */ + ret = nct6694_read_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPO_DIR + data->group, + sizeof(data->reg_val), + &data->reg_val); + if (ret < 0) + return ret; + + data->reg_val |= BIT(offset); + ret = nct6694_write_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPO_DIR + data->group, + sizeof(data->reg_val), + &data->reg_val); + if (ret < 0) + return ret; + + /* Then set output level */ + ret = nct6694_read_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPO_DATA + data->group, + sizeof(data->reg_val), + &data->reg_val); + if (ret < 0) + return ret; + + if (val) + data->reg_val |= BIT(offset); + else + data->reg_val &= ~BIT(offset); + + return nct6694_write_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPO_DATA + data->group, + sizeof(data->reg_val), + &data->reg_val); +} + +static int nct6694_get_value(struct gpio_chip *gpio, unsigned int offset) +{ + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); + int ret; + + guard(mutex)(&data->lock); + + ret = nct6694_read_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPO_DIR + data->group, + sizeof(data->reg_val), + &data->reg_val); + if (ret < 0) + return ret; + + if (BIT(offset) & data->reg_val) { + ret = nct6694_read_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPO_DATA + data->group, + sizeof(data->reg_val), + &data->reg_val); + if (ret < 0) + return ret; + + return !!(BIT(offset) & data->reg_val); + } + + ret = nct6694_read_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPI_DATA + data->group, + sizeof(data->reg_val), + &data->reg_val); + if (ret < 0) + return ret; + + return !!(BIT(offset) & data->reg_val); +} + +static void nct6694_set_value(struct gpio_chip *gpio, unsigned int offset, + int val) +{ + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); + + guard(mutex)(&data->lock); + + nct6694_read_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPO_DATA + data->group, + sizeof(data->reg_val), + &data->reg_val); + + if (val) + data->reg_val |= BIT(offset); + else + data->reg_val &= ~BIT(offset); + + nct6694_write_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPO_DATA + data->group, + sizeof(data->reg_val), + &data->reg_val); +} + +static int nct6694_set_config(struct gpio_chip *gpio, unsigned int offset, + unsigned long config) +{ + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); + int ret; + + guard(mutex)(&data->lock); + + ret = nct6694_read_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPO_TYPE + data->group, + sizeof(data->reg_val), + &data->reg_val); + if (ret < 0) + return ret; + + switch (pinconf_to_config_param(config)) { + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + data->reg_val |= BIT(offset); + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + data->reg_val &= ~BIT(offset); + break; + default: + return -ENOTSUPP; + } + + return nct6694_write_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPO_TYPE + data->group, + sizeof(data->reg_val), + &data->reg_val); +} + +static int nct6694_init_valid_mask(struct gpio_chip *gpio, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); + int ret; + + guard(mutex)(&data->lock); + + ret = nct6694_read_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPIO_VALID + data->group, + sizeof(data->reg_val), + &data->reg_val); + if (ret < 0) + return ret; + + *valid_mask = data->reg_val; + + return ret; +} + +static irqreturn_t nct6694_irq_handler(int irq, void *priv) +{ + struct nct6694_gpio_data *data = priv; + unsigned char status; + + guard(mutex)(&data->lock); + + nct6694_read_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPI_STS + data->group, + sizeof(data->reg_val), + &data->reg_val); + + status = data->reg_val; + + while (status) { + int bit = __ffs(status); + + data->reg_val = BIT(bit); + handle_nested_irq(irq_find_mapping(data->gpio.irq.domain, bit)); + status &= ~BIT(bit); + nct6694_write_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPI_CLR + data->group, + sizeof(data->reg_val), + &data->reg_val); + } + + return IRQ_HANDLED; +} + +static int nct6694_get_irq_trig(struct nct6694_gpio_data *data) +{ + int ret; + + guard(mutex)(&data->lock); + + ret = nct6694_read_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPI_FALLING + data->group, + sizeof(data->irq_trig_falling), + &data->irq_trig_falling); + if (ret) + return ret; + + return nct6694_read_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPI_RISING + data->group, + sizeof(data->irq_trig_rising), + &data->irq_trig_rising); +} + +static void nct6694_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gpio = irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); + + gpiochip_disable_irq(gpio, hwirq); +} + +static void nct6694_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gpio = irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq = irqd_to_hwirq(d); + + gpiochip_enable_irq(gpio, hwirq); +} + +static int nct6694_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gpio = irq_data_get_irq_chip_data(d); + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); + irq_hw_number_t hwirq = irqd_to_hwirq(d); + + guard(mutex)(&data->lock); + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + data->irq_trig_rising |= BIT(hwirq); + break; + + case IRQ_TYPE_EDGE_FALLING: + data->irq_trig_falling |= BIT(hwirq); + break; + + case IRQ_TYPE_EDGE_BOTH: + data->irq_trig_rising |= BIT(hwirq); + data->irq_trig_falling |= BIT(hwirq); + break; + + default: + return -ENOTSUPP; + } + + return 0; +} + +static void nct6694_irq_bus_lock(struct irq_data *d) +{ + struct gpio_chip *gpio = irq_data_get_irq_chip_data(d); + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); + + mutex_lock(&data->irq_lock); +} + +static void nct6694_irq_bus_sync_unlock(struct irq_data *d) +{ + struct gpio_chip *gpio = irq_data_get_irq_chip_data(d); + struct nct6694_gpio_data *data = gpiochip_get_data(gpio); + + scoped_guard(mutex, &data->lock) { + nct6694_write_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPI_FALLING + data->group, + sizeof(data->irq_trig_falling), + &data->irq_trig_falling); + + nct6694_write_msg(data->nct6694, NCT6694_GPIO_MOD, + NCT6694_GPI_RISING + data->group, + sizeof(data->irq_trig_rising), + &data->irq_trig_rising); + } + + mutex_unlock(&data->irq_lock); +} + +static const struct irq_chip nct6694_irq_chip = { + .name = "nct6694-gpio", + .irq_mask = nct6694_irq_mask, + .irq_unmask = nct6694_irq_unmask, + .irq_set_type = nct6694_irq_set_type, + .irq_bus_lock = nct6694_irq_bus_lock, + .irq_bus_sync_unlock = nct6694_irq_bus_sync_unlock, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static int nct6694_gpio_probe(struct platform_device *pdev) +{ + const struct mfd_cell *cell = mfd_get_cell(pdev); + struct device *dev = &pdev->dev; + struct nct6694 *nct6694 = dev_get_drvdata(pdev->dev.parent); + struct nct6694_gpio_data *data; + struct gpio_irq_chip *girq; + int ret, irq, i; + char **names; + + irq = irq_create_mapping(nct6694->domain, + NCT6694_IRQ_GPIO0 + cell->id); + if (!irq) + return -EINVAL; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + names = devm_kcalloc(dev, NCT6694_NR_GPIO, sizeof(char *), + GFP_KERNEL); + if (!names) + return -ENOMEM; + + for (i = 0; i < NCT6694_NR_GPIO; i++) { + names[i] = devm_kasprintf(dev, GFP_KERNEL, "GPIO%X%d", + cell->id, i); + if (!names[i]) + return -ENOMEM; + } + + data->nct6694 = nct6694; + data->group = cell->id; + + data->gpio.names = (const char * const*)names; + data->gpio.label = pdev->name; + data->gpio.direction_input = nct6694_direction_input; + data->gpio.get = nct6694_get_value; + data->gpio.direction_output = nct6694_direction_output; + data->gpio.set = nct6694_set_value; + data->gpio.get_direction = nct6694_get_direction; + data->gpio.set_config = nct6694_set_config; + data->gpio.init_valid_mask = nct6694_init_valid_mask; + data->gpio.base = -1; + data->gpio.can_sleep = false; + data->gpio.owner = THIS_MODULE; + data->gpio.ngpio = NCT6694_NR_GPIO; + + devm_mutex_init(dev, &data->lock); + devm_mutex_init(dev, &data->irq_lock); + + ret = nct6694_get_irq_trig(data); + if (ret) + return dev_err_probe(dev, ret, "Failed to get irq trigger type\n"); + + girq = &data->gpio.irq; + gpio_irq_chip_set_chip(girq, &nct6694_irq_chip); + girq->parent_handler = NULL; + girq->num_parents = 0; + girq->parents = NULL; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + girq->threaded = true; + + ret = devm_request_threaded_irq(dev, irq, NULL, nct6694_irq_handler, + IRQF_ONESHOT | IRQF_SHARED, + "nct6694-gpio", data); + if (ret) + return dev_err_probe(dev, ret, "Failed to request irq\n"); + + return devm_gpiochip_add_data(dev, &data->gpio, data); +} + +static struct platform_driver nct6694_gpio_driver = { + .driver = { + .name = "nct6694-gpio", + }, + .probe = nct6694_gpio_probe, +}; + +module_platform_driver(nct6694_gpio_driver); + +MODULE_DESCRIPTION("USB-GPIO controller driver for NCT6694"); +MODULE_AUTHOR("Ming Yu <tmyu0@nuvoton.com>"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:nct6694-gpio");

[v4,2/7] gpio: Add Nuvoton NCT6694 GPIO support

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