| Message ID | 20241219142216.2123065-1-jon.lin@rock-chips.com |
|---|---|
| State | Accepted |
| Commit | af103eb7d7d881cf6ff7414242bce2d8e394cc32 |
| Headers | show |
| Series | spi: rockchip-sfc: Support sclk_x2 version | expand |
On Thu, 19 Dec 2024 22:22:16 +0800, Jon Lin wrote: > SFC after version 8 supports dtr mode, so the IO is the binary output of > the controller clock. > > Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [1/1] spi: rockchip-sfc: Support sclk_x2 version commit: af103eb7d7d881cf6ff7414242bce2d8e394cc32 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
diff --git a/drivers/spi/spi-rockchip-sfc.c b/drivers/spi/spi-rockchip-sfc.c index 36509bcccc27..59de351499a0 100644 --- a/drivers/spi/spi-rockchip-sfc.c +++ b/drivers/spi/spi-rockchip-sfc.c @@ -112,6 +112,7 @@ #define SFC_VER_3 0x3 #define SFC_VER_4 0x4 #define SFC_VER_5 0x5 +#define SFC_VER_8 0x8 /* Delay line controller register */ #define SFC_DLL_CTRL0 0x3C @@ -217,6 +218,22 @@ static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) return SFC_MAX_IOSIZE_VER3; } +static int rockchip_sfc_clk_set_rate(struct rockchip_sfc *sfc, unsigned long speed) +{ + if (sfc->version >= SFC_VER_8) + return clk_set_rate(sfc->clk, speed * 2); + else + return clk_set_rate(sfc->clk, speed); +} + +static unsigned long rockchip_sfc_clk_get_rate(struct rockchip_sfc *sfc) +{ + if (sfc->version >= SFC_VER_8) + return clk_get_rate(sfc->clk) / 2; + else + return clk_get_rate(sfc->clk); +} + static void rockchip_sfc_irq_unmask(struct rockchip_sfc *sfc, u32 mask) { u32 reg; @@ -519,12 +536,12 @@ static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op if (unlikely(mem->spi->max_speed_hz != sfc->speed[cs]) && !has_acpi_companion(sfc->dev)) { - ret = clk_set_rate(sfc->clk, mem->spi->max_speed_hz); + ret = rockchip_sfc_clk_set_rate(sfc, mem->spi->max_speed_hz); if (ret) goto out; sfc->speed[cs] = mem->spi->max_speed_hz; dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n", - sfc->speed[cs], clk_get_rate(sfc->clk)); + sfc->speed[cs], rockchip_sfc_clk_get_rate(sfc)); } rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
SFC after version 8 supports dtr mode, so the IO is the binary output of the controller clock. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> --- drivers/spi/spi-rockchip-sfc.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-)