| Message ID | 20241211-add_usb_host_mode_for_qcs615-v2-2-2c4abdf67635@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: qcom: Add DT support for secondary USB on QCS615 | expand |
On Thu, Dec 12, 2024 at 07:14:22PM +0100, Konrad Dybcio wrote: > On 11.12.2024 9:26 AM, Song Xue wrote: > > From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> > > > > Enable secondary USB controller on QCS615 Ride platform. The secondary > > USB controller is made "host", as it is a Type-A port. > > > > Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> > > Co-developed-by: Song Xue <quic_songxue@quicinc.com> > > Signed-off-by: Song Xue <quic_songxue@quicinc.com> > > --- > > arch/arm64/boot/dts/qcom/qcs615-ride.dts | 28 ++++++++++++++++++++++++++++ > > 1 file changed, 28 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts > > index f41319ff47b983d771da52775fa78b4385c4e532..26ce0496d13ccbfea392c6d50d9edcab85fbc653 100644 > > --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts > > +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts > > @@ -203,6 +203,15 @@ &gcc { > > <&sleep_clk>; > > }; > > > > +&pm8150_gpios { > > + usb2_en_state: usb2-en-state { > > + pins = "gpio10"; > > + function = "normal"; > > + output-high; > > + power-source = <0>; > > + }; > > Does this go to an enable pin of a vreg / switch? > > I think we settled on describing such cases as fixed regulators > (that are always-on for now) - would you remember, +Dmitry? You are right. Usually it's a fixed regulator. At least there should be an explanation for that pin. > > The rest looks good. > > Konrad
On 12/13/2024 2:14 AM, Konrad Dybcio wrote: > On 11.12.2024 9:26 AM, Song Xue wrote: >> From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> >> >> Enable secondary USB controller on QCS615 Ride platform. The secondary >> USB controller is made "host", as it is a Type-A port. >> >> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> >> Co-developed-by: Song Xue <quic_songxue@quicinc.com> >> Signed-off-by: Song Xue <quic_songxue@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 28 ++++++++++++++++++++++++++++ >> 1 file changed, 28 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >> index f41319ff47b983d771da52775fa78b4385c4e532..26ce0496d13ccbfea392c6d50d9edcab85fbc653 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts >> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >> @@ -203,6 +203,15 @@ &gcc { >> <&sleep_clk>; >> }; >> >> +&pm8150_gpios { >> + usb2_en_state: usb2-en-state { >> + pins = "gpio10"; >> + function = "normal"; >> + output-high; >> + power-source = <0>; >> + }; > > Does this go to an enable pin of a vreg / switch? Thanks for comment. We go to enable the pin of PMIC chip. The pin of PMIC is connecting to host-enable pin of USB converter. Need pin of PMIC chip to be high level, when USB is as host mode. > > I think we settled on describing such cases as fixed regulators > (that are always-on for now) - would you remember, +Dmitry? > > The rest looks good. > > Konrad
On Fri, 13 Dec 2024 at 08:59, Song Xue <quic_songxue@quicinc.com> wrote: > > > > On 12/13/2024 2:14 AM, Konrad Dybcio wrote: > > On 11.12.2024 9:26 AM, Song Xue wrote: > >> From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> > >> > >> Enable secondary USB controller on QCS615 Ride platform. The secondary > >> USB controller is made "host", as it is a Type-A port. > >> > >> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> > >> Co-developed-by: Song Xue <quic_songxue@quicinc.com> > >> Signed-off-by: Song Xue <quic_songxue@quicinc.com> > >> --- > >> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 28 ++++++++++++++++++++++++++++ > >> 1 file changed, 28 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts > >> index f41319ff47b983d771da52775fa78b4385c4e532..26ce0496d13ccbfea392c6d50d9edcab85fbc653 100644 > >> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts > >> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts > >> @@ -203,6 +203,15 @@ &gcc { > >> <&sleep_clk>; > >> }; > >> > >> +&pm8150_gpios { > >> + usb2_en_state: usb2-en-state { > >> + pins = "gpio10"; > >> + function = "normal"; > >> + output-high; > >> + power-source = <0>; > >> + }; > > > > Does this go to an enable pin of a vreg / switch? > > Thanks for comment. > We go to enable the pin of PMIC chip. The pin of PMIC is connecting to > host-enable pin of USB converter. Need pin of PMIC chip to be high > level, when USB is as host mode. What kind of USB converter are we talking about? > > > > I think we settled on describing such cases as fixed regulators > > (that are always-on for now) - would you remember, +Dmitry? > > > > The rest looks good. > > > > Konrad >
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index f41319ff47b983d771da52775fa78b4385c4e532..26ce0496d13ccbfea392c6d50d9edcab85fbc653 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -203,6 +203,15 @@ &gcc { <&sleep_clk>; }; +&pm8150_gpios { + usb2_en_state: usb2-en-state { + pins = "gpio10"; + function = "normal"; + output-high; + power-source = <0>; + }; +}; + &pon_pwrkey { status = "okay"; }; @@ -248,6 +257,25 @@ &usb_1_dwc3 { dr_mode = "peripheral"; }; +&usb_hsphy_2 { + vdd-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + vdda-phy-dpdm-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_2 { + pinctrl-0 = <&usb2_en_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + &watchdog { clocks = <&sleep_clk>; };