@@ -761,8 +761,10 @@ RMIF 1 01 11010000 imm:6 00001 rn:5 0 mask:4
SETF8 0 01 11010000 00000 000010 rn:5 01101
SETF16 0 01 11010000 00000 010010 rn:5 01101
-# Conditional compare (regster)
-# Conditional compare (immediate)
+# Conditional compare
+
+CCMP sf:1 op:1 1 11010010 y:5 cond:4 imm:1 0 rn:5 0 nzcv:4
+
# Conditional select
# Data Processing (3-source)
@@ -8092,68 +8092,46 @@ static bool do_setf(DisasContext *s, int rn, int shift)
TRANS_FEAT(SETF8, aa64_condm_4, do_setf, a->rn, 24)
TRANS_FEAT(SETF16, aa64_condm_4, do_setf, a->rn, 16)
-/* Conditional compare (immediate / register)
- * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
- * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
- * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
- * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
- * [1] y [0] [0]
- */
-static void disas_cc(DisasContext *s, uint32_t insn)
+/* CCMP, CCMN */
+static bool trans_CCMP(DisasContext *s, arg_CCMP *a)
{
- unsigned int sf, op, y, cond, rn, nzcv, is_imm;
- TCGv_i32 tcg_t0, tcg_t1, tcg_t2;
- TCGv_i64 tcg_tmp, tcg_y, tcg_rn;
+ TCGv_i32 tcg_t0 = tcg_temp_new_i32();
+ TCGv_i32 tcg_t1 = tcg_temp_new_i32();
+ TCGv_i32 tcg_t2 = tcg_temp_new_i32();
+ TCGv_i64 tcg_tmp = tcg_temp_new_i64();
+ TCGv_i64 tcg_rn, tcg_y;
DisasCompare c;
-
- if (!extract32(insn, 29, 1)) {
- unallocated_encoding(s);
- return;
- }
- if (insn & (1 << 10 | 1 << 4)) {
- unallocated_encoding(s);
- return;
- }
- sf = extract32(insn, 31, 1);
- op = extract32(insn, 30, 1);
- is_imm = extract32(insn, 11, 1);
- y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */
- cond = extract32(insn, 12, 4);
- rn = extract32(insn, 5, 5);
- nzcv = extract32(insn, 0, 4);
+ unsigned nzcv;
/* Set T0 = !COND. */
- tcg_t0 = tcg_temp_new_i32();
- arm_test_cc(&c, cond);
+ arm_test_cc(&c, a->cond);
tcg_gen_setcondi_i32(tcg_invert_cond(c.cond), tcg_t0, c.value, 0);
/* Load the arguments for the new comparison. */
- if (is_imm) {
- tcg_y = tcg_temp_new_i64();
- tcg_gen_movi_i64(tcg_y, y);
+ if (a->imm) {
+ tcg_y = tcg_constant_i64(a->y);
} else {
- tcg_y = cpu_reg(s, y);
+ tcg_y = cpu_reg(s, a->y);
}
- tcg_rn = cpu_reg(s, rn);
+ tcg_rn = cpu_reg(s, a->rn);
/* Set the flags for the new comparison. */
- tcg_tmp = tcg_temp_new_i64();
- if (op) {
- gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y);
+ if (a->op) {
+ gen_sub_CC(a->sf, tcg_tmp, tcg_rn, tcg_y);
} else {
- gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y);
+ gen_add_CC(a->sf, tcg_tmp, tcg_rn, tcg_y);
}
- /* If COND was false, force the flags to #nzcv. Compute two masks
+ /*
+ * If COND was false, force the flags to #nzcv. Compute two masks
* to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
* For tcg hosts that support ANDC, we can make do with just T1.
* In either case, allow the tcg optimizer to delete any unused mask.
*/
- tcg_t1 = tcg_temp_new_i32();
- tcg_t2 = tcg_temp_new_i32();
tcg_gen_neg_i32(tcg_t1, tcg_t0);
tcg_gen_subi_i32(tcg_t2, tcg_t0, 1);
+ nzcv = a->nzcv;
if (nzcv & 8) { /* N */
tcg_gen_or_i32(cpu_NF, cpu_NF, tcg_t1);
} else {
@@ -8190,6 +8168,7 @@ static void disas_cc(DisasContext *s, uint32_t insn)
tcg_gen_and_i32(cpu_VF, cpu_VF, tcg_t2);
}
}
+ return true;
}
/* Conditional select
@@ -8266,10 +8245,6 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
}
switch (op2) {
- case 0x2: /* Conditional compare */
- disas_cc(s, insn); /* both imm and reg forms */
- break;
-
case 0x4: /* Conditional select */
disas_cond_select(s, insn);
break;
@@ -8277,6 +8252,7 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
default:
do_unallocated:
case 0x0:
+ case 0x2: /* Conditional compare */
case 0x6: /* Data-processing */
case 0x8 ... 0xf: /* (3 source) */
unallocated_encoding(s);