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[PULL,58/72] target/riscv: Set default NaN pattern explicitly

Message ID 20241211162004.2795499-59-peter.maydell@linaro.org
State Accepted
Commit 3d3d399e76c204c718f3ec6ef48fd0bb303070ab
Headers show
Series [PULL,01/72] hw/net/lan9118: Extract lan9118_phy | expand

Commit Message

Peter Maydell Dec. 11, 2024, 4:19 p.m. UTC 
Set the default NaN pattern explicitly for riscv.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241202131347.498124-53-peter.maydell@linaro.org
---
 target/riscv/cpu.c | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f219f0c3b52..80b09952e78 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1022,6 +1022,8 @@  static void riscv_cpu_reset_hold(Object *obj, ResetType type)
     cs->exception_index = RISCV_EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
+    /* Default NaN value: sign bit clear, frac msb set */
+    set_float_default_nan_pattern(0b01000000, &env->fp_status);
     env->vill = true;
 
 #ifndef CONFIG_USER_ONLY