@@ -7805,96 +7805,65 @@ static bool do_xpac(DisasContext *s, int rd, NeonGenOne64OpEnvFn *fn)
TRANS_FEAT(XPACI, aa64_pauth, do_xpac, a->rd, gen_helper_xpaci)
TRANS_FEAT(XPACD, aa64_pauth, do_xpac, a->rd, gen_helper_xpacd)
-/* Logical (shifted register)
- * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
- * +----+-----+-----------+-------+---+------+--------+------+------+
- * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
- * +----+-----+-----------+-------+---+------+--------+------+------+
- */
-static void disas_logic_reg(DisasContext *s, uint32_t insn)
+static bool do_logic_reg(DisasContext *s, arg_logic_shift *a,
+ ArithTwoOp *fn, ArithTwoOp *inv_fn, bool setflags)
{
TCGv_i64 tcg_rd, tcg_rn, tcg_rm;
- unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd;
- sf = extract32(insn, 31, 1);
- opc = extract32(insn, 29, 2);
- shift_type = extract32(insn, 22, 2);
- invert = extract32(insn, 21, 1);
- rm = extract32(insn, 16, 5);
- shift_amount = extract32(insn, 10, 6);
- rn = extract32(insn, 5, 5);
- rd = extract32(insn, 0, 5);
-
- if (!sf && (shift_amount & (1 << 5))) {
- unallocated_encoding(s);
- return;
+ if (!a->sf && (a->sa & (1 << 5))) {
+ return false;
}
- tcg_rd = cpu_reg(s, rd);
+ tcg_rd = cpu_reg(s, a->rd);
+ tcg_rn = cpu_reg(s, a->rn);
- if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) {
- /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
- * register-register MOV and MVN, so it is worth special casing.
- */
- tcg_rm = cpu_reg(s, rm);
- if (invert) {
+ tcg_rm = read_cpu_reg(s, a->rm, a->sf);
+ if (a->sa) {
+ shift_reg_imm(tcg_rm, tcg_rm, a->sf, a->st, a->sa);
+ }
+
+ (a->n ? inv_fn : fn)(tcg_rd, tcg_rn, tcg_rm);
+ if (!a->sf) {
+ tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
+ }
+ if (setflags) {
+ gen_logic_CC(a->sf, tcg_rd);
+ }
+ return true;
+}
+
+static bool trans_ORR_r(DisasContext *s, arg_logic_shift *a)
+{
+ /*
+ * Unshifted ORR and ORN with WZR/XZR is the standard encoding for
+ * register-register MOV and MVN, so it is worth special casing.
+ */
+ if (a->sa == 0 && a->st == 0 && a->rn == 31) {
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ TCGv_i64 tcg_rm = cpu_reg(s, a->rm);
+
+ if (a->n) {
tcg_gen_not_i64(tcg_rd, tcg_rm);
- if (!sf) {
+ if (!a->sf) {
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
} else {
- if (sf) {
+ if (a->sf) {
tcg_gen_mov_i64(tcg_rd, tcg_rm);
} else {
tcg_gen_ext32u_i64(tcg_rd, tcg_rm);
}
}
- return;
+ return true;
}
- tcg_rm = read_cpu_reg(s, rm, sf);
-
- if (shift_amount) {
- shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount);
- }
-
- tcg_rn = cpu_reg(s, rn);
-
- switch (opc | (invert << 2)) {
- case 0: /* AND */
- case 3: /* ANDS */
- tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm);
- break;
- case 1: /* ORR */
- tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm);
- break;
- case 2: /* EOR */
- tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm);
- break;
- case 4: /* BIC */
- case 7: /* BICS */
- tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm);
- break;
- case 5: /* ORN */
- tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm);
- break;
- case 6: /* EON */
- tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm);
- break;
- default:
- assert(FALSE);
- break;
- }
-
- if (!sf) {
- tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
- }
-
- if (opc == 3) {
- gen_logic_CC(sf, tcg_rd);
- }
+ return do_logic_reg(s, a, tcg_gen_or_i64, tcg_gen_orc_i64, false);
}
+TRANS(AND_r, do_logic_reg, a, tcg_gen_and_i64, tcg_gen_andc_i64, false)
+TRANS(ANDS_r, do_logic_reg, a, tcg_gen_and_i64, tcg_gen_andc_i64, true)
+TRANS(EOR_r, do_logic_reg, a, tcg_gen_xor_i64, tcg_gen_eqv_i64, false)
+
/*
* Add/subtract (extended register)
*
@@ -8411,11 +8380,9 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
/* Add/sub (shifted register) */
disas_add_sub_reg(s, insn);
}
- } else {
- /* Logical (shifted register) */
- disas_logic_reg(s, insn);
+ return;
}
- return;
+ goto do_unallocated;
}
switch (op2) {
@@ -716,6 +716,15 @@ XPACI 1 10 11010110 00001 010000 11111 rd:5
XPACD 1 10 11010110 00001 010001 11111 rd:5
# Logical (shifted reg)
+
+&logic_shift rd rn rm sf sa st n
+@logic_shift sf:1 .. ..... st:2 n:1 rm:5 sa:6 rn:5 rd:5
+
+AND_r . 00 01010 .. . ..... ...... ..... ..... @logic_shift
+ORR_r . 01 01010 .. . ..... ...... ..... ..... @logic_shift
+EOR_r . 10 01010 .. . ..... ...... ..... ..... @logic_shift
+ANDS_r . 11 01010 .. . ..... ...... ..... ..... @logic_shift
+
# Add/subtract (shifted reg)
# Add/subtract (extended reg)
# Add/subtract (carry)
This includes AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS (shifted reg). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/tcg/translate-a64.c | 117 ++++++++++++--------------------- target/arm/tcg/a64.decode | 9 +++ 2 files changed, 51 insertions(+), 75 deletions(-)