| Message ID | 20241127-correct_timer_irq-v1-1-ce4309b655bd@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: qcom: Correct IRQ number of EL2 non-secure physical timer | expand |
On 11/27/2024 5:37 PM, Krzysztof Kozlowski wrote: > On 27/11/2024 10:32, Cong Zhang wrote: >> The INTID of EL2 non-secure physical timer is 26. In linux, the IRQ >> number has a fixed 16 offset for PPIs. Therefore, the linux IRQ number >> of EL2 non-secure physical timer should be 10 (26 - 16). >> >> Signed-off-by: Cong Zhang <quic_congzhan@quicinc.com> >> --- >> The EL2 non-secure physical timer is utilized during kernel bootup in >> EL2 mode with KVM enabled. This patch has been verified on the QCS8300 >> platform with KVM enabled. Given that the dependency patch has already >> been reviewed, I am uncertain whether it is preferable to submit this >> fix as a new patch or to combine it with the dependency patch. I would >> appreciate your suggestions on this patch. >> --- >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 2 +- > This was not merged. Do not post fixes to things which are still patches > on mailing list. > > Best regards, > Krzysztof Thanks for your suggestion. The patches for qcs8300 are update https://lore.kernel.org/all/20241128-qcs8300_initial_dtsi-v3-3-26aa8a164914@quicinc.com/. I will update this patch to fix sdx75 platform which is already merged.
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 2c35f96c3f289d5e2e57e0e30ef5e17cd1286188..de6c368efb3a5efeaf628babdb7e91f8cbbf9d5f 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -1370,6 +1370,6 @@ arch_timer: timer { interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 5f7e59ecf1ca6298cb252ee0654bc7eaeefbd303..b0775173278f3eed0f301b40dfba0f2680d7b0d0 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -1548,6 +1548,6 @@ timer { interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; };
The INTID of EL2 non-secure physical timer is 26. In linux, the IRQ number has a fixed 16 offset for PPIs. Therefore, the linux IRQ number of EL2 non-secure physical timer should be 10 (26 - 16). Signed-off-by: Cong Zhang <quic_congzhan@quicinc.com> --- The EL2 non-secure physical timer is utilized during kernel bootup in EL2 mode with KVM enabled. This patch has been verified on the QCS8300 platform with KVM enabled. Given that the dependency patch has already been reviewed, I am uncertain whether it is preferable to submit this fix as a new patch or to combine it with the dependency patch. I would appreciate your suggestions on this patch. --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) --- base-commit: 6ad9d5070ae9de51803b16ffc384c23d62466c7d change-id: 20241126-correct_timer_irq-133e0a33e792 prerequisite-message-id: <20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com> prerequisite-patch-id: 73c78f31fa1d504124d4a82b578a6a14126cccd8 prerequisite-patch-id: 5a01283c8654ae7c696d9c69cb21505b71c5ca27 prerequisite-patch-id: dc633d5aaac790776a8a213ea2faa4890a3f665d prerequisite-patch-id: 9ecf4cb8b5842ac64e51d6baa0e6c1fbe449ee66 Best regards,