| Message ID | 20241127-dp_dts_qcs8300-v1-1-e3d13dec4233@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Enable Display Port for Qualcomm QCS8300-ride platform | expand |
On 2024/12/6 5:36, Konrad Dybcio wrote: > On 27.11.2024 11:45 AM, Yongxing Mou wrote: >> Add device tree nodes for the DPTX0 controller with their >> corresponding PHYs found on Qualcomm QCS8300 SoC. >> >> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 115 +++++++++++++++++++++++++++++++++- >> 1 file changed, 114 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> index 1642e2863affd5af0b4f68118a47b7a74b76df95..28deba0a389641b4dddbf4505d6f44c6607aa03b 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> @@ -987,6 +987,19 @@ mdss_mdp: display-controller@ae01000 { >> interrupt-parent = <&mdss>; >> interrupts = <0>; >> >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + >> + dpu_intf0_out: endpoint { >> + remote-endpoint = <&mdss_dp0_in>; >> + }; >> + }; >> + }; >> + >> mdp_opp_table: opp-table { >> compatible = "operating-points-v2"; >> >> @@ -1011,6 +1024,104 @@ opp-650000000 { >> }; >> }; >> }; >> + >> + mdss_dp0_phy: phy@aec2a00 { >> + compatible = "qcom,qcs8300-edp-phy"; >> + >> + reg = <0x0 0x0aec2a00 0x0 0x200>, > > 0x19c > got it.thanks. >> + <0x0 0x0aec2200 0x0 0xd0>, > > 0xec got it.thanks. >> + <0x0 0x0aec2600 0x0 0xd0>, > > 0xec > > For lengths got it.thanks. > >> + <0x0 0x0aec2000 0x0 0x1c8>; > > This one's correct > >> + >> + clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, >> + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; >> + clock-names = "aux", >> + "cfg_ahb"; > > power-domains = <&rpmhpd RPMHPD_MX>; > emm,we use RPMHPD_MMCX in qcs8300 mdss and dpu.. > (or maybe even MXC?) > >> + >> + #clock-cells = <1>; >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + mdss_dp0: displayport-controller@af54000 { >> + compatible = "qcom,qcs8300-dp"; >> + >> + reg = <0x0 0x0af54000 0x0 0x104>, > 0x200 > got it. thanks. >> + <0x0 0x0af54200 0x0 0x0c0>, > 0x200 > got it. thanks. >> + <0x0 0x0af55000 0x0 0x770>, > 0xc00 > got it. thanks. >> + <0x0 0x0af56000 0x0 0x09c>; > 0x400 > will modify all the length in patch v2. > for lengths > > Konrad
On Thu, Dec 26, 2024 at 03:03:46PM +0800, Yongxing Mou wrote: > > > On 2024/12/6 5:36, Konrad Dybcio wrote: > > On 27.11.2024 11:45 AM, Yongxing Mou wrote: > > > > > + > > > + clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, > > > + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; > > > + clock-names = "aux", > > > + "cfg_ahb"; > > > > power-domains = <&rpmhpd RPMHPD_MX>; > > > emm,we use RPMHPD_MMCX in qcs8300 mdss and dpu.. > > (or maybe even MXC?) But it is a DP PHY, not a MDSS or DPU. Is the PLL being sourced by MMCX or by MX?
On 26.12.2024 8:03 AM, Yongxing Mou wrote: > > > On 2024/12/6 5:36, Konrad Dybcio wrote: >> On 27.11.2024 11:45 AM, Yongxing Mou wrote: >>> Add device tree nodes for the DPTX0 controller with their >>> corresponding PHYs found on Qualcomm QCS8300 SoC. >>> >>> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> >>> --- [...] >>> + mdss_dp0_phy: phy@aec2a00 { >>> + compatible = "qcom,qcs8300-edp-phy"; >>> + >>> + reg = <0x0 0x0aec2a00 0x0 0x200>, >> >> 0x19c >> > got it.thanks. >>> + <0x0 0x0aec2200 0x0 0xd0>, >> >> 0xec > got it.thanks. >>> + <0x0 0x0aec2600 0x0 0xd0>, >> >> 0xec >> >> For lengths > got it.thanks. >> >>> + <0x0 0x0aec2000 0x0 0x1c8>; >> >> This one's correct >> >>> + >>> + clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, >>> + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; >>> + clock-names = "aux", >>> + "cfg_ahb"; >> >> power-domains = <&rpmhpd RPMHPD_MX>; >> > emm,we use RPMHPD_MMCX in qcs8300 mdss and dpu.. >> (or maybe even MXC?) Please verify what backs the PHY and update accordingly Konrad
On Wed, Nov 27, 2024 at 06:45:13PM +0800, Yongxing Mou wrote: > Add device tree nodes for the DPTX0 controller with their > corresponding PHYs found on Qualcomm QCS8300 SoC. > > Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> Please rebase, test and resubmit this together, in the same series, with the mdss patch. Regards, Bjorn > --- > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 115 +++++++++++++++++++++++++++++++++- > 1 file changed, 114 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > index 1642e2863affd5af0b4f68118a47b7a74b76df95..28deba0a389641b4dddbf4505d6f44c6607aa03b 100644 > --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > @@ -987,6 +987,19 @@ mdss_mdp: display-controller@ae01000 { > interrupt-parent = <&mdss>; > interrupts = <0>; > > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + dpu_intf0_out: endpoint { > + remote-endpoint = <&mdss_dp0_in>; > + }; > + }; > + }; > + > mdp_opp_table: opp-table { > compatible = "operating-points-v2"; > > @@ -1011,6 +1024,104 @@ opp-650000000 { > }; > }; > }; > + > + mdss_dp0_phy: phy@aec2a00 { > + compatible = "qcom,qcs8300-edp-phy"; > + > + reg = <0x0 0x0aec2a00 0x0 0x200>, > + <0x0 0x0aec2200 0x0 0xd0>, > + <0x0 0x0aec2600 0x0 0xd0>, > + <0x0 0x0aec2000 0x0 0x1c8>; > + > + clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, > + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; > + clock-names = "aux", > + "cfg_ahb"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + mdss_dp0: displayport-controller@af54000 { > + compatible = "qcom,qcs8300-dp"; > + > + reg = <0x0 0x0af54000 0x0 0x104>, > + <0x0 0x0af54200 0x0 0x0c0>, > + <0x0 0x0af55000 0x0 0x770>, > + <0x0 0x0af56000 0x0 0x09c>; > + > + interrupt-parent = <&mdss>; > + interrupts = <12>; > + > + clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, > + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, > + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, > + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, > + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; > + clock-names = "core_iface", > + "core_aux", > + "ctrl_link", > + "ctrl_link_iface", > + "stream_pixel"; > + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, > + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&mdss_dp0_phy 0>, > + <&mdss_dp0_phy 1>; > + phys = <&mdss_dp0_phy>; > + phy-names = "dp"; > + > + operating-points-v2 = <&dp_opp_table>; > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + > + #sound-dai-cells = <0>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + mdss_dp0_in: endpoint { > + remote-endpoint = <&dpu_intf0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + mdss_dp0_out: endpoint { }; > + }; > + }; > + > + dp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-160000000 { > + opp-hz = /bits/ 64 <160000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > }; > > dispcc: clock-controller@af00000 { > @@ -1020,7 +1131,9 @@ dispcc: clock-controller@af00000 { > <&rpmhcc RPMH_CXO_CLK>, > <&rpmhcc RPMH_CXO_CLK_A>, > <&sleep_clk>, > - <0>, <0>, <0>, <0>, > + <&mdss_dp0_phy 0>, > + <&mdss_dp0_phy 1>, > + <0>, <0>, > <0>, <0>, <0>, <0>; > power-domains = <&rpmhpd RPMHPD_MMCX>; > #clock-cells = <1>; > > -- > 2.34.1 >
On 2024/12/27 3:57, Dmitry Baryshkov wrote: > On Thu, Dec 26, 2024 at 03:03:46PM +0800, Yongxing Mou wrote: >> >> >> On 2024/12/6 5:36, Konrad Dybcio wrote: >>> On 27.11.2024 11:45 AM, Yongxing Mou wrote: >>> >>>> + >>>> + clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, >>>> + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; >>>> + clock-names = "aux", >>>> + "cfg_ahb"; >>> >>> power-domains = <&rpmhpd RPMHPD_MX>; >>> >> emm,we use RPMHPD_MMCX in qcs8300 mdss and dpu.. >>> (or maybe even MXC?) > > But it is a DP PHY, not a MDSS or DPU. Is the PLL being sourced by MMCX > or by MX? > Hi, thank for pointing it.We confirm it, and this should use RPMHPD_MX not RPMHPD_MMCX.
On 2025/1/9 7:06, Bjorn Andersson wrote: > On Wed, Nov 27, 2024 at 06:45:13PM +0800, Yongxing Mou wrote: >> Add device tree nodes for the DPTX0 controller with their >> corresponding PHYs found on Qualcomm QCS8300 SoC. >> >> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> > > Please rebase, test and resubmit this together, in the same series, with > the mdss patch. > > Regards, > Bjorn > sure. got it. I will integrate the mdss dts change with this and submit it together.thanks. >> --- >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 115 +++++++++++++++++++++++++++++++++- >> 1 file changed, 114 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> index 1642e2863affd5af0b4f68118a47b7a74b76df95..28deba0a389641b4dddbf4505d6f44c6607aa03b 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> @@ -987,6 +987,19 @@ mdss_mdp: display-controller@ae01000 { >> interrupt-parent = <&mdss>; >> interrupts = <0>; >> >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + >> + dpu_intf0_out: endpoint { >> + remote-endpoint = <&mdss_dp0_in>; >> + }; >> + }; >> + }; >> + >> mdp_opp_table: opp-table { >> compatible = "operating-points-v2"; >> >> @@ -1011,6 +1024,104 @@ opp-650000000 { >> }; >> }; >> }; >> + >> + mdss_dp0_phy: phy@aec2a00 { >> + compatible = "qcom,qcs8300-edp-phy"; >> + >> + reg = <0x0 0x0aec2a00 0x0 0x200>, >> + <0x0 0x0aec2200 0x0 0xd0>, >> + <0x0 0x0aec2600 0x0 0xd0>, >> + <0x0 0x0aec2000 0x0 0x1c8>; >> + >> + clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, >> + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; >> + clock-names = "aux", >> + "cfg_ahb"; >> + >> + #clock-cells = <1>; >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + mdss_dp0: displayport-controller@af54000 { >> + compatible = "qcom,qcs8300-dp"; >> + >> + reg = <0x0 0x0af54000 0x0 0x104>, >> + <0x0 0x0af54200 0x0 0x0c0>, >> + <0x0 0x0af55000 0x0 0x770>, >> + <0x0 0x0af56000 0x0 0x09c>; >> + >> + interrupt-parent = <&mdss>; >> + interrupts = <12>; >> + >> + clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, >> + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, >> + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, >> + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, >> + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; >> + clock-names = "core_iface", >> + "core_aux", >> + "ctrl_link", >> + "ctrl_link_iface", >> + "stream_pixel"; >> + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, >> + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; >> + assigned-clock-parents = <&mdss_dp0_phy 0>, >> + <&mdss_dp0_phy 1>; >> + phys = <&mdss_dp0_phy>; >> + phy-names = "dp"; >> + >> + operating-points-v2 = <&dp_opp_table>; >> + power-domains = <&rpmhpd RPMHPD_MMCX>; >> + >> + #sound-dai-cells = <0>; >> + >> + status = "disabled"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + >> + mdss_dp0_in: endpoint { >> + remote-endpoint = <&dpu_intf0_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + >> + mdss_dp0_out: endpoint { }; >> + }; >> + }; >> + >> + dp_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-160000000 { >> + opp-hz = /bits/ 64 <160000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-270000000 { >> + opp-hz = /bits/ 64 <270000000>; >> + required-opps = <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-540000000 { >> + opp-hz = /bits/ 64 <540000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; >> + }; >> + >> + opp-810000000 { >> + opp-hz = /bits/ 64 <810000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> + }; >> }; >> >> dispcc: clock-controller@af00000 { >> @@ -1020,7 +1131,9 @@ dispcc: clock-controller@af00000 { >> <&rpmhcc RPMH_CXO_CLK>, >> <&rpmhcc RPMH_CXO_CLK_A>, >> <&sleep_clk>, >> - <0>, <0>, <0>, <0>, >> + <&mdss_dp0_phy 0>, >> + <&mdss_dp0_phy 1>, >> + <0>, <0>, >> <0>, <0>, <0>, <0>; >> power-domains = <&rpmhpd RPMHPD_MMCX>; >> #clock-cells = <1>; >> >> -- >> 2.34.1 >>
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 1642e2863affd5af0b4f68118a47b7a74b76df95..28deba0a389641b4dddbf4505d6f44c6607aa03b 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -987,6 +987,19 @@ mdss_mdp: display-controller@ae01000 { interrupt-parent = <&mdss>; interrupts = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + }; + mdp_opp_table: opp-table { compatible = "operating-points-v2"; @@ -1011,6 +1024,104 @@ opp-650000000 { }; }; }; + + mdss_dp0_phy: phy@aec2a00 { + compatible = "qcom,qcs8300-edp-phy"; + + reg = <0x0 0x0aec2a00 0x0 0x200>, + <0x0 0x0aec2200 0x0 0xd0>, + <0x0 0x0aec2600 0x0 0xd0>, + <0x0 0x0aec2000 0x0 0x1c8>; + + clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", + "cfg_ahb"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,qcs8300-dp"; + + reg = <0x0 0x0af54000 0x0 0x104>, + <0x0 0x0af54200 0x0 0x0c0>, + <0x0 0x0af55000 0x0 0x770>, + <0x0 0x0af56000 0x0 0x09c>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_dp0_phy 0>, + <&mdss_dp0_phy 1>; + phys = <&mdss_dp0_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; }; dispcc: clock-controller@af00000 { @@ -1020,7 +1131,9 @@ dispcc: clock-controller@af00000 { <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <0>, <0>, <0>, + <&mdss_dp0_phy 0>, + <&mdss_dp0_phy 1>, + <0>, <0>, <0>, <0>, <0>, <0>; power-domains = <&rpmhpd RPMHPD_MMCX>; #clock-cells = <1>;
Add device tree nodes for the DPTX0 controller with their corresponding PHYs found on Qualcomm QCS8300 SoC. Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 115 +++++++++++++++++++++++++++++++++- 1 file changed, 114 insertions(+), 1 deletion(-)