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[PULL,7/9] docs/system/arm/: add FEAT_DoubleLock

Message ID 20241126170224.2926917-8-peter.maydell@linaro.org
State Accepted
Commit e8319a32271c0a8a25f2a6a55b6612629634b4cd
Headers show
Series [PULL,1/9] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names | expand

Commit Message

Peter Maydell Nov. 26, 2024, 5:02 p.m. UTC 
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>

We already implement FEAT_DoubleLock (see commit f94a6df5dd6a7) when
the ID registers call for it.  This feature is actually one that must
*not* be implemented in v9.0, but since our documentation lists
everything we can emulate, we should include FEAT_DoubleLock in the
list.

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-id: 20241122225049.1617774-7-pierrick.bouvier@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: expand commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 47f5123a31d..38534dcdd32 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -37,6 +37,7 @@  the following architecture extensions:
 - FEAT_CSV3 (Cache speculation variant 3)
 - FEAT_DGH (Data gathering hint)
 - FEAT_DIT (Data Independent Timing instructions)
+- FEAT_DoubleLock (Double Lock)
 - FEAT_DPB (DC CVAP instruction)
 - FEAT_DPB2 (DC CVADP instruction)
 - FEAT_Debugv8p1 (Debug with VHE)