| Message ID | 20241126140003.74871-9-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/mips: Convert nanoMIPS LSA opcode to decodetree | expand |
On 11/26/24 07:59, Philippe Mathieu-Daudé wrote: > From: Philippe Mathieu-Daudé <f4bug@amsat.org> > > Introduce the microMIPS decodetree configs for the 16-bit > and 32-bit instructions. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/mips/tcg/translate.h | 2 ++ > target/mips/tcg/micromips16.decode | 11 +++++++++++ > target/mips/tcg/micromips32.decode | 11 +++++++++++ > target/mips/tcg/micromips_translate.c | 14 ++++++++++++++ > target/mips/tcg/micromips_translate.c.inc | 9 +++++++++ > target/mips/tcg/meson.build | 3 +++ > 6 files changed, 50 insertions(+) > create mode 100644 target/mips/tcg/micromips16.decode > create mode 100644 target/mips/tcg/micromips32.decode > create mode 100644 target/mips/tcg/micromips_translate.c > > diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h > index d1aa811cfa1..2a079cb28d9 100644 > --- a/target/mips/tcg/translate.h > +++ b/target/mips/tcg/translate.h > @@ -222,6 +222,8 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); > bool decode_64bit_enabled(DisasContext *ctx); > > /* decodetree generated */ > +bool decode_isa_micromips16(DisasContext *ctx, uint16_t insn); > +bool decode_isa_micromips32(DisasContext *ctx, uint32_t insn); > bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); > bool decode_ase_mips16e_16(DisasContext *ctx, uint16_t insn); > bool decode_ase_mips16e_32(DisasContext *ctx, uint32_t insn); > diff --git a/target/mips/tcg/micromips16.decode b/target/mips/tcg/micromips16.decode > new file mode 100644 > index 00000000000..d341da16b04 > --- /dev/null > +++ b/target/mips/tcg/micromips16.decode > @@ -0,0 +1,11 @@ > +# microMIPS32 16-bit instruction set extensions > +# > +# Copyright (C) 2021 Philippe Mathieu-Daudé > +# > +# SPDX-License-Identifier: LGPL-2.1-or-later > +# > +# Reference: MIPS Architecture for Programmers, Volume II-B > +# microMIPS32 Instruction Set > +# (Document Number: MD00582) > +# microMIPS64 Instruction Set > +# (Document Number: MD00594) > diff --git a/target/mips/tcg/micromips32.decode b/target/mips/tcg/micromips32.decode > new file mode 100644 > index 00000000000..333ab0969ca > --- /dev/null > +++ b/target/mips/tcg/micromips32.decode > @@ -0,0 +1,11 @@ > +# microMIPS32 32-bit instruction set extensions > +# > +# Copyright (C) 2021 Philippe Mathieu-Daudé > +# > +# SPDX-License-Identifier: LGPL-2.1-or-later > +# > +# Reference: MIPS Architecture for Programmers, Volume II-B > +# microMIPS32 Instruction Set > +# (Document Number: MD00582) > +# microMIPS64 Instruction Set > +# (Document Number: MD00594) > diff --git a/target/mips/tcg/micromips_translate.c b/target/mips/tcg/micromips_translate.c > new file mode 100644 > index 00000000000..49e90e7eca2 > --- /dev/null > +++ b/target/mips/tcg/micromips_translate.c > @@ -0,0 +1,14 @@ > +/* > + * MIPS emulation for QEMU - microMIPS translation routines > + * > + * Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org> > + * > + * SPDX-License-Identifier: LGPL-2.1-or-later > + */ > + > +#include "qemu/osdep.h" > +#include "translate.h" > + > +/* Include the auto-generated decoders. */ > +#include "decode-micromips16.c.inc" > +#include "decode-micromips32.c.inc" > diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc > index 26006f84df7..7a884222eed 100644 > --- a/target/mips/tcg/micromips_translate.c.inc > +++ b/target/mips/tcg/micromips_translate.c.inc > @@ -3018,6 +3018,15 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) > } > } > > + if (decode_isa_micromips16(ctx, opcode)) { > + return 2; > + } > + opcode <<= 16; > + opcode |= translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); > + if (decode_isa_micromips32(ctx, opcode)) { > + return 4; > + } In the switch just above, you have determined 16-bit vs 32-bit, have you not? I think you should make use of that and keep these two cases separate. r~
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index d1aa811cfa1..2a079cb28d9 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -222,6 +222,8 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); bool decode_64bit_enabled(DisasContext *ctx); /* decodetree generated */ +bool decode_isa_micromips16(DisasContext *ctx, uint16_t insn); +bool decode_isa_micromips32(DisasContext *ctx, uint32_t insn); bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_mips16e_16(DisasContext *ctx, uint16_t insn); bool decode_ase_mips16e_32(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/tcg/micromips16.decode b/target/mips/tcg/micromips16.decode new file mode 100644 index 00000000000..d341da16b04 --- /dev/null +++ b/target/mips/tcg/micromips16.decode @@ -0,0 +1,11 @@ +# microMIPS32 16-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: MIPS Architecture for Programmers, Volume II-B +# microMIPS32 Instruction Set +# (Document Number: MD00582) +# microMIPS64 Instruction Set +# (Document Number: MD00594) diff --git a/target/mips/tcg/micromips32.decode b/target/mips/tcg/micromips32.decode new file mode 100644 index 00000000000..333ab0969ca --- /dev/null +++ b/target/mips/tcg/micromips32.decode @@ -0,0 +1,11 @@ +# microMIPS32 32-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: MIPS Architecture for Programmers, Volume II-B +# microMIPS32 Instruction Set +# (Document Number: MD00582) +# microMIPS64 Instruction Set +# (Document Number: MD00594) diff --git a/target/mips/tcg/micromips_translate.c b/target/mips/tcg/micromips_translate.c new file mode 100644 index 00000000000..49e90e7eca2 --- /dev/null +++ b/target/mips/tcg/micromips_translate.c @@ -0,0 +1,14 @@ +/* + * MIPS emulation for QEMU - microMIPS translation routines + * + * Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org> + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" + +/* Include the auto-generated decoders. */ +#include "decode-micromips16.c.inc" +#include "decode-micromips32.c.inc" diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index 26006f84df7..7a884222eed 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -3018,6 +3018,15 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) } } + if (decode_isa_micromips16(ctx, opcode)) { + return 2; + } + opcode <<= 16; + opcode |= translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); + if (decode_isa_micromips32(ctx, opcode)) { + return 4; + } + switch (op) { case POOL16A: { diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index bcb64368be8..ca70769912c 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,6 +1,8 @@ gen = [ decodetree.process('mips16e_16.decode', extra_args: ['--decode=decode_ase_mips16e_16', '--insnwidth=16']), decodetree.process('mips16e_32.decode', extra_args: ['--decode=decode_ase_mips16e_32']), + decodetree.process('micromips16.decode', extra_args: ['--decode=decode_isa_micromips16', '--insnwidth=16']), + decodetree.process('micromips32.decode', extra_args: ['--decode=decode_isa_micromips32']), decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), @@ -18,6 +20,7 @@ mips_ss.add(files( 'fpu_helper.c', 'ldst_helper.c', 'lmmi_helper.c', + 'micromips_translate.c', 'mips16e_translate.c', 'msa_helper.c', 'msa_translate.c',