| Message ID | 20241126131546.66145-11-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/mips: Simplify some target_ulong registers to 32-bit | expand |
On 11/26/24 07:15, Philippe Mathieu-Daudé wrote: > Similarly to the gen_move_high32_tl() helper which sign-extract > the 32-higher bits of a target-wide TCG register, add a helper > to sign-extract from 32-bit TCG registers. Similarly wrt "sign-extract" and "from". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 11/26/24 07:15, Philippe Mathieu-Daudé wrote: > Similarly to the gen_move_high32_tl() helper which sign-extract > the 32-higher bits of a target-wide TCG register, add a helper > to sign-extract from 32-bit TCG registers. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/mips/tcg/translate.h | 1 + > target/mips/tcg/translate.c | 5 +++++ > 2 files changed, 6 insertions(+) > > diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h > index d5d74faad92..f974cf29297 100644 > --- a/target/mips/tcg/translate.h > +++ b/target/mips/tcg/translate.h > @@ -156,6 +156,7 @@ void gen_base_offset_addr_tl(DisasContext *ctx, TCGv addr, int base, int offset) > void gen_move_low32_tl(TCGv ret, TCGv_i64 arg); > void gen_move_low32_i32(TCGv_i32 ret, TCGv_i64 arg); > void gen_move_high32_tl(TCGv ret, TCGv_i64 arg); > +void gen_move_high32_i32(TCGv_i32 ret, TCGv_i64 arg); > void gen_load_gpr_tl(TCGv t, int reg); > void gen_load_gpr_i32(TCGv_i32 t, int reg); > void gen_store_gpr_tl(TCGv t, int reg); > diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c > index 80e2a8e5256..d6be37d56d3 100644 > --- a/target/mips/tcg/translate.c > +++ b/target/mips/tcg/translate.c > @@ -1494,6 +1494,11 @@ void gen_move_high32_tl(TCGv ret, TCGv_i64 arg) > #endif > } > > +void gen_move_high32_i32(TCGv_i32 ret, TCGv_i64 arg) > +{ > + tcg_gen_extrh_i64_i32(ret, arg); > +} > + Actually, I don't see a need for either of these. Why not use the tcg_gen_* functions directly? Indeed, the combined tcg_gen_extr_i64_i32(low, high, arg) in most places. r~
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index d5d74faad92..f974cf29297 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -156,6 +156,7 @@ void gen_base_offset_addr_tl(DisasContext *ctx, TCGv addr, int base, int offset) void gen_move_low32_tl(TCGv ret, TCGv_i64 arg); void gen_move_low32_i32(TCGv_i32 ret, TCGv_i64 arg); void gen_move_high32_tl(TCGv ret, TCGv_i64 arg); +void gen_move_high32_i32(TCGv_i32 ret, TCGv_i64 arg); void gen_load_gpr_tl(TCGv t, int reg); void gen_load_gpr_i32(TCGv_i32 t, int reg); void gen_store_gpr_tl(TCGv t, int reg); diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 80e2a8e5256..d6be37d56d3 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1494,6 +1494,11 @@ void gen_move_high32_tl(TCGv ret, TCGv_i64 arg) #endif } +void gen_move_high32_i32(TCGv_i32 ret, TCGv_i64 arg) +{ + tcg_gen_extrh_i64_i32(ret, arg); +} + bool check_cp0_enabled(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
Similarly to the gen_move_high32_tl() helper which sign-extract the 32-higher bits of a target-wide TCG register, add a helper to sign-extract from 32-bit TCG registers. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/mips/tcg/translate.h | 1 + target/mips/tcg/translate.c | 5 +++++ 2 files changed, 6 insertions(+)